Date of Award

5-2007

Degree Type

Dissertation

Degree Name

Doctor of Philosophy

Major

Electrical Engineering

Major Professor

Syed Kamrul Islam

Committee Members

Benjamin J. Blalock, Charles L. Britton, Jr., Xiaobing Feng

Abstract

In Radio Frequency (RF) integrated circuit design field, programmable dividers are getting more and more attentions in recent years. A programmable frequency divider can divide an input frequency by programmable ratios [1]. It is a key component of a frequency synthesizer. It also can be used to generate variable clock-signals for: switched-capacitor filters (SCFs), digital systems with different power-states, as well as multiple clock-signals on the same system-on-a-chip (SOC). These circuits need high performance programmable frequency dividers, operating at high frequencies and having wide division ratio ranges, with binary division ratio controls and 50% output duty-cycle.

Different types of programmable frequency dividers are reviewed and compared. A programmable frequency divider with a wide division ratio range of (8 ~ 524287) has been reported [2]. Because the output duty-cycle of this reported divider is far from 50%, the circuit in [2] has very limited applications. The proposed design solves this problem, without compromising other advantages of the design in [2]. The proposed design is fabricated in a 0.18-μm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. The duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant, with different input frequencies from GHz down to kHz ranges, with different temperatures and power supply voltages. This thesis provides an explanation of the design details and test results.

A Phase Locked-Loop (PLL) based frequency synthesizer can generate different output frequencies. A programmable frequency divider is an important component of this type of PLL. Since bandwidth is expensive, it is preferred to reduce the frequency channel distance of a frequency synthesizer. Using a fractional programmable divider, the frequency channel distance of a PLL can be reduced, without reducing the reference frequency or increasing the settling time of the PLL. A frequency synthesizer with a programmable fractional divider is designed and fabricated. A brief description of the PLL design and test results are presented in this dissertation.

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