MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR A Dissertation Presented for the Doctor of Philosophy Degree The University of Tennessee, Knoxville Md Sakib Hasan August 2017 ii DEDICATION This dissertation is dedicated to my parents, Zahir Uddin Ahmed and Shirin Akhter Lovely. iii ACKNOWLEDGMENTS I would like to express my earnest gratitude to my advisor Dr. Syed K. Islam for all the help and guidance he has provided me throughout my years of graduate study. His advice on matters, both technical and non-technical, has taught me how to grow as a successful engineer. Without his constant encouragement and direction, this journey would not have been possible. Special thanks go to Dr. Benjamin J. Blalock for his guidance and support as well as for the excellent courses he taught. I have benefited greatly from the conversations we had about circuit design and G4FET. I would like to extend my gratitude to Dr. Nicole McFarlane for serving on my committee and for her insightful suggestions about improving the work. I would also like to thank Dr. Ramakrishnan Kalyanaraman for finding time from his busy schedule to serve on my Ph.D. committee. I am grateful to The Institute of Biomedical Engineering at the University of Tennessee and the Min H. Kao Department of Electrical Engineering and Computer Science at the University of Tennessee, Knoxville for their financial support. I have had the good fortune of benefiting from important discussions with various people which have helped me a lot in my research. I would specially like to thank Ifana Mahbub, Khandakar Abdullah Al Mamun, Md Habibullah Habib, Riyasat Azim, Ishtiaque Hossain and Shamim Ara for making my graduate life enjoyable. Finally, I would like to express my deepest gratitude to my parents, Zahir Uddin Ahmed and Shirin Akhter Lovely, my brother Rajib Hasan and my friends Arunodoy, Avijit, Shibani, Himadri, Zisan, Farah, Babu bhai, Sanjib , Dulal, Ratna and Monir vai. iv ABSTRACT As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and v provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET. vi TABLE OF CONTENTS Chapter 1 – Introduction ............................................................................................................. 1 1.1 Motivation ........................................................................................................................................................... 1 1.2 Research Goal ..................................................................................................................................................... 5 1.3 Dissertation Overview ........................................................................................................................................ 6 Chapter 2 - Literature Review ..................................................................................................... 7 2.1 Previous Works on G4FET .................................................................................................................................. 7 2.2 Previous Works on Numerical Modeling .......................................................................................................... 10 2.3 Previous Works on Macromodels ..................................................................................................................... 13 2.4 Previous Works on Physics-based Compact Modeling ..................................................................................... 15 Chapter 3 - Device Structure and Operating Mechanism of G4FET ..................................... 21 3.1 Multiple Independent Gate Silicon-On-Insulator (SOI) Transistor................................................................... 21 3.2 G4FET Device Structure ................................................................................................................................... 23 3.3 Principle of Operation ....................................................................................................................................... 24 3.4 Effect of Gate Bias on Conduction Path ........................................................................................................... 26 3.5 Chapter Summary ............................................................................................................................................. 29 Chapter 4 - Numerical Modeling of G4FET ............................................................................. 30 4.1 Overview ........................................................................................................................................................... 30 4.2 Numerical Method 1 (Multivariate Lagrange Interpolation Polynomial Model) .............................................. 31 4.2.1 Model Formulation ................................................................................................................................... 31 4.2.2 Model Validation ....................................................................................................................................... 34 4.2.2.1 An n-Channel G4FET Simulated with TCAD Sentaurus (Device 1) ................................................................... 34 4.2.2.2 Experimental Data from an n-Channel G4FET (Device 2) .................................................................................. 37 4.2.2.3 A p-Channel G4FET Simulated Using TCAD Sentaurus (Device 3) .................................................................. 39 vii 4.2.2.4 Experimental Data from a p-Channel G4FET (Device 4) .................................................................................... 42 4.2.2.5 Incorporation of Device Geometry ...................................................................................................................... 45 4.2.2.6 First Order Characteristics i.e. Transconductance and Drain Output Resistance ................................................ 46 4.2.3 Implementation in Circuit Simulator ......................................................................................................... 46 4.2.4 Results from G4FET Circuit Simulation .................................................................................................... 49 4.3 Numerical Method 2 (Multidimensional Bernstein Polynomial Model) .......................................................... 52 4.3.1 Model Formulation ................................................................................................................................... 52 4.3.2 Model Validation ....................................................................................................................................... 53 4.3.2.1 An n-Channel G4FET Simulated Using TCAD Sentaurus (Device 1) ................................................................ 53 4.3.2.2 Experimental Data from an n-Channel G4FET (Device 2) .................................................................................. 55 4.3.2.3 A p-Channel G4FET Simulated Using TCAD Sentaurus (Device 3) .................................................................. 57 4.3.2.4 Experimental Data from a p-Channel G4FET (Device 4) .................................................................................... 58 4.3.2.5 Incorporation of Device Geometry ...................................................................................................................... 60 4.3.2.6 First Order Characteristics i.e. Transconductance and Drain Output Resistance ................................................ 60 4.4 Numerical Method 3 (Multivariate Regression Polynomial Model) ................................................................. 63 4.4.1 Model Formulation ................................................................................................................................... 63 4.4.2 Model Validation ....................................................................................................................................... 65 4.4.2.1 An n-Channel G4FET Simulated Using TCAD Sentaurus (Device 1) ................................................................ 65 4.4.2.2 Experimental Data from an n-Channel G4FET (Device 2) .................................................................................. 69 4.4.2.3 A p-Channel G4FET Simulated Using TCAD Sentaurus (Device 3) .................................................................. 72 4.4.2.4 Experimental Data from a p-Channel G4FET (Device 4) .................................................................................... 76 4.4.2.5 Modeling of Device Geometry ............................................................................................................................ 79 4.4.2.6 First Order Characteristics (Device Transconductance and Drain Output Resistance) ....................................... 81 4.4.3 Circuit Simulator (SPICE and SpectreTM) Implementation ....................................................................... 83 4.4.4 Results from G4FET Circuit Simulation .................................................................................................... 84 4.5 Numerical method 4 (Multidimensional Linear and Cubic Spline Interpolation Model) ................................. 86 4.5.1 Model Formulation ................................................................................................................................... 87 4.5.1.1 Linear Spline Model ............................................................................................................................................ 87 4.5.1.2 Cubic Spline Model............................................................................................................................................. 88 viii 4.5.2 Model Validation ....................................................................................................................................... 89 4.5.2.1 An n-Channel G4FET Simulated Using TCAD Sentaurus (Device 1) ................................................................ 89 4.5.2.2 Experimental Data from an n-Channel G4FET (Device 2) .................................................................................. 91 4.5.2.3 A p-Channel G4FET Simulated with TCAD Sentaurus (Device 3) ..................................................................... 93 4.5.2.4 Experimental Data from a p-Channel G4FET (Device 4) .................................................................................... 95 4.5.2.5 Incorporation of Device Geometry ...................................................................................................................... 96 4.5.2.6 Validation of First Order Characteristics i.e. Device Transconductance and Output Drain Resistance .............. 97 4.5.3 Implementation in Circuit Simulator ......................................................................................................... 99 4.5.4 Results from G4FET Circuit Simulation .................................................................................................. 100 4.5.4.1 Negative Differential Resistance (NDR) LC oscillator: .................................................................................... 100 4.5.4.2 High Voltage Differential Amplifier ................................................................................................................. 101 4.5.4.3 Four-Quadrant Analog Multiplier: .................................................................................................................... 102 4.6 Chapter Summary ........................................................................................................................................... 109 Chapter 5 - Macromodel of G4FET ......................................................................................... 111 5.1 Motivation ....................................................................................................................................................... 111 5.2 Model Formation ............................................................................................................................................ 111 5.3 CAD Implementation for Circuit Design ........................................................................................................ 113 5.3.1 Negative Differential Resistance Circuit: ............................................................................................... 114 5.3.2 Differential Amplifier: ............................................................................................................................. 115 5.3.3 Four Quadrant Analog Multiplier : ........................................................................................................ 116 5.3.4 Multi-Threshold Inverter: ....................................................................................................................... 122 5.3.5 Universal and Programmable Gate: ....................................................................................................... 122 5.3.6 Full Adder: .............................................................................................................................................. 124 5.4 Chapter Summary ........................................................................................................................................... 127 Chapter 6 – Physics-Based Compact Model of G4FET ......................................................... 128 6.1 Motivation ....................................................................................................................................................... 128 6.2 Depletion All Around (DAA) Model .............................................................................................................. 128 ix 6.2.1 Model Formulation ................................................................................................................................. 129 6.2.2 Model Validation ..................................................................................................................................... 131 6.3 Front Surface Accumulation Model ................................................................................................................ 134 6.3.1 Model Formulation ................................................................................................................................. 135 6.3.2 Model Validation ..................................................................................................................................... 136 6.4 Chapter Summary ........................................................................................................................................... 139 Chapter 7 - Conclusion and Future Work .............................................................................. 140 7.1 Original Contributions .................................................................................................................................... 140 7.2 Dissertation Summary ..................................................................................................................................... 142 7.3 Future Works .................................................................................................................................................. 143 References .................................................................................................................................. 145 Vita …………………………………………………………………………………………….160 x LIST OF TABLES Table 4.1: Geometry, Doping and Biasing for an n-Channel G4FET ........................................... 35 Table 4.2: Geometry, Doping and Biasing for a p-Channel G4FET ............................................. 40 Table 4.3: Computational Complexity of Lagrange Model .......................................................... 48 Table 4.4: Computational Complexity of Regression Model ....................................................... 83 Table 4.5: Comparison Between Experimental and Simulation Results for DC Transfer Characteristics of Configuration 1 ...................................................................................... 106 Table 4.6: Comparison Between Experimental rand Simulation Results for DC Transfer Characteristics of Configuration 2 ...................................................................................... 106 Table 5.1: Comparison Between Experimental and Simulation Results (Macromodel) for DC Transfer Characteristics of Analog Multiplier (Configuration 1) ....................................... 119 Table 5.2: Comparison of Experimental and Simulation Results (Macromodel) for DC Transfer Characteristics of Analog Multiplier (Configuration 2) ..................................................... 119 Table 5.3: Truth Table of a Full Adder ....................................................................................... 126 xi LIST OF FIGURES Figure 1.1: Moore’s Law dictating transistor counts in microprocessor over the years [9]. .......... 2 Figure 1.2: Change of direction in gate length scaling from 2013 to 2015 ITRS report [13]. ....... 3 Figure 1.3: Possible alternatives for extending Moore’s law . ....................................................... 4 Figure 3.1: Three layers of SOI wafer. ......................................................................................... 21 Figure 3.2: Cross-sectional schematic of a fully depleted (FD) SOI device. ............................... 22 Figure 3.3: Cross-sectional schematic of a partially depleted (PD) SOI. ..................................... 22 Figure 3.4: 3-D Schematic of a G4FET structure. ......................................................................... 25 Figure 3.5: G4FET structure: (a) cross section and (b) top view. ................................................. 25 Figure 3.6: Electron density in the top silicon film at VTG = 0 V, VBG = 0 V and VJG = 0 V. ...... 27 Figure 3.7: Electron density in the top silicon film at VTG = -3 V, VBG = 0 V and VJG = 0 V. ..... 27 Figure 3.8: Electron density in the top silicon film at VTG = 0 V VBG = -3 V VJG = 0 V. .............. 27 Figure 3.9: Electron density in the top silicon film at VTG = -3 V, VBG = -3 V and VJG = 0 V. ..... 28 Figure 3.10: Electron density in the top silicon film at VTG = 0 V, VBG = 0 V and VJG = -1 V. ... 28 Figure 3.11: Electron density in the top silicon film at VTG = 3 V, VBG = 0 V and VJG = 0 V. .... 28 Figure 3.12: Electron density in the top silicon film at VTG = 3 V, VBG = 10 V and VJG = 0 V. ... 29 Figure 4.1: Drain current versus drain-source voltage from TCAD data and Lagrange model for different orders of VDS for an n-channel G4FET. .................................................................. 36 Figure 4.2: Relative errors between TCAD data and Lagrange model for different orders of VDS for an n-channel G4FET. ............................................................................................................. 36 Figure 4.3: Isolines of test data and model for different junction-gate voltages ranging from -4 V to 0 V in 1 V increment with order of VDS fixed at 8. ........................................................... 37 xii Figure 4.4: Drain current versus top-gate voltage from experimental data and Lagrange model for different orders of VTG for an n-channel G4FET (Device 2). ................................................ 38 Figure 4.5: Relative errors in model prediction for different orders of VTG for an n-channel G4FET (Device 2). ............................................................................................................................. 38 Figure 4.6: Comparison between isolines of test data and Lagrange model for different bottom- gate voltages ranging from -4 V to 4 V in 2 V increment with the model order for VTG fixed at 7 (Device 2). ...................................................................................................................... 39 Figure 4.7: Drain current versus source-drain voltage from TCAD data and Lagrange model for different orders of VSD for a p-channel G4FET (Device 3). .................................................. 41 Figure 4.8: Relative errors between TCAD data and Lagrange model for different orders of VSD for a p-channel G4FET (Device 3). ....................................................................................... 41 Figure 4.9: Drain current versus source-drain voltage for different junction-gate voltages ranging from 0 V to 4 V in 1 V increment and corresponding mean relative error (Device 3). ........ 42 Figure 4.10: Comparison of ID-VTG between experimental data and Lagrange model for different orders of VTG for a p-Channel G4FET (Device 4). ................................................................ 43 Figure 4.11: Relative errors between experimental data and Lagrange model for different orders of VTG for a p-Channel G4FET (Device 4). ........................................................................... 44 Figure 4.12: Comparison between isolines of test data and model (10th order VTG ) for different junction-gate voltages ranging from 0.6 V to 1.8 V in 0.4 V increment arranged from top to bottom (Device 4). ............................................................................................................... 44 Figure 4.13: Comparison of drain current versus drain-source voltage between TCAD data and Lagrange model of test geometry for different orders. ......................................................... 45 xiii Figure 4.14: Relative errors between TCAD data and Lagrange model of test geometry for different orders. .................................................................................................................................... 46 Figure 4.15: Comparison of gm – VTG between experimental data and Lagrange model for different orders of VTG for a p-channel G4FET (Device 4). ................................................................. 47 Figure 4.16: Comparison of rout - VDS between TCAD data and Lagrange model for different orders of VDS for an n-channel G4FET (Device 1). .......................................................................... 47 Figure 4.17: Behavioral model of an n-channel G4FET. .............................................................. 49 Figure 4.18: (a) A conventional two-terminal JFET NDR device, (b) a four-terminal G4FET NDR device. ................................................................................................................................... 50 Figure 4.19: A simplified symbol of G4FET NDR. ...................................................................... 50 Figure 4.20: An LC oscillator using G4-NDR. ............................................................................. 51 Figure 4.21: (a) Output from SPICE simulator (769 kHz signal with 2.47 Vp-p amplitude), (b) experimental result (768 kHz with 2.5 Vp-p amplitude). ....................................................... 51 Figure 4.22: Drain current versus drain-source voltage from TCAD data and Bernstein model for different orders of VDS in an n-channel G4FET (Device 1). .................................................. 54 Figure 4.23: Relative errors between TCAD data and Bernstein model for different orders of VDS for an n-channel G4FET (Device 1). ..................................................................................... 55 Figure 4.24: Drain current versus top-gate voltage from experimental data and Bernstein model for different orders of VTG for an n-channel G4FET (Device 2). .......................................... 56 Figure 4.25: Relative errors between experimental data and Bernstein model for different orders of VTG for an n-channel G4FET (Device 2). .......................................................................... 56 Figure 4.26: Comparison of ID-VSD between TCAD data and Bernstein model for different orders of VSD for a p-channel G4FET (Device 3). ............................................................................ 57 xiv Figure 4.27: Relative errors between TCAD data and Bernstein model for different orders of VSD for a p-channel G4FET (Device 3). ....................................................................................... 58 Figure 4.28: Comparison of ISD-VTG between experimental data and Bernstein model for different orders of VTG for a p-channel G4FET (Device 4). ................................................................. 59 Figure 4.29: Relative errors between experimental data and Bernstein model for different orders of VTG for a p-channel G4FET (Device 4). ............................................................................ 59 Figure 4.30: Drain current versus drain-source voltage from TCAD data and Bernstein model of different orders for test geometry. ........................................................................................ 61 Figure 4.31: Relative errors between TCAD data and Bernstein model for test geometry. ......... 61 Figure 4.32: Transconductance versus top-gate voltage from experimental data and Bernstein model for different orders of VTG for a p-channel G4FET (Device 4). ................................. 62 Figure 4.33: Output resistance versus drain-source voltage from TCAD data and Bernstein model for different orders of VDS for an n-channel G4FET (Device 1). ........................................... 63 Figure 4.34: Comparison of IDS-VDS between TCAD data and regression model for different orders of VDS with order of VBG fixed at 3 for an n-channel G4FET. ............................................... 66 Figure 4.35: Relative error between TCAD data and regression model for different orders of VDS with VBG fixed at 3 for an n-channel G4FET. ........................................................................ 67 Figure 4.36: Comparison of IDS-VDS between TCAD data and regression model for different orders of VDS with order of VBG fixed at 4 for an n-channel G4FET. ............................................... 67 Figure 4.37: Relative error between TCAD data and regression model for different orders of VDS with order of VBG fixed at 4 for an n-channel G4FET. .......................................................... 68 xv Figure 4.38: Comparison between isolines of test data and regression model (order of VDS, VBG, VTG, VJG respectively 10, 4, 5 and 5) for different junction-gate voltages ranging from -4 V to 0 V in 1 V increment arranged from bottom to top. ............................................................. 68 Figure 4.39: Comparison of IDS-VTG between experimental data and regression model for different orders of VTG with the order of VBG and VJG fixed at 2. ........................................................ 70 Figure 4.40: Relative error between experimental data and regression model for different orders of VTG with the order of VBG and VJG fixed at 2. ................................................................... 70 Figure 4.41: Comparison of IDS -VTG between experimental data and regression model for different orders of VTG with the order of VJG and VBG fixed at 2 and 4, respectively. ......................... 71 Figure 4.42: Relative error between experimental data and regression model for different orders of VTG with the order of VJG and VBG fixed at 2 and 4, respectively. .................................... 71 Figure 4.43: Comparison between isolines of test data and regression model (order of VBG, VTG, VJG respectively 3, 8 and 2) for different bottom-gate voltages ranging from -4 V to 4 V in 2 V increment arranged from bottom to top. ........................................................................... 72 Figure 4.44: Comparison of ISD-VSD between TCAD data and regression model for different orders of VSD with order of VTG fixed at 4 for a p-channel G4FET. ................................................. 73 Figure 4.45: Relative error between TCAD data and regression model for different orders of VSD with order of VTG fixed at 4 for a p-channel G4FET. ............................................................ 74 Figure 4.46: Comparison of ISD-VDS between TCAD data and regression model for different orders of VSD with order of VTG fixed at 5 for a p-channel G4FET. ................................................. 74 Figure 4.47: Relative error between TCAD data and regression model for different orders of VSD with order of VTG fixed at 5 for a p-channel G4FET. ............................................................ 75 xvi Figure 4.48: Comparison between isolines of test data and regression model for different junction- gate voltages ranging from 0 V to 4 V in 1 V increment (Device 3). ................................... 75 Figure 4.49: Comparison of ISD-VTG between p-G4FET experimental data and regression model for different orders of VTG with the order of VJG fixed at 3. ....................................................... 77 Figure 4.50: Relative error between p-G4FET experimental data and regression model for different orders of VTG with the order of VJG fixed at 3. ...................................................................... 77 Figure 4.51: Comparison of ISD-VTG between p-G4FET experimental data and regression model for different orders of VTG with the order of VJG fixed at 6. ....................................................... 78 Figure 4.52: Relative error between p-G4FET experimental data and regression model for different orders of VTG with the order of VJG fixed at 6. ...................................................................... 78 Figure 4.53: Comparison between isolines of test data and regression model for different junction- gate voltages ranging from 0.2 V to 1.4 V in 0.4 V increment (Device 4). .......................... 79 Figure 4.54: Comparison of drain current versus drain-source voltage between TCAD data and regression model for different orders of VDS for test geometry. ........................................... 80 Figure 4.55: Relative errors between TCAD data and regression model for different orders of VDS for test geometry. .................................................................................................................. 80 Figure 4.56: Comparison between TCAD data and regression model of isolines for different widths ranging from 0.3 to 0.5 µm in .05 µm increment arranged from bottom to top. .................. 81 Figure 4.57: Comparison of gm–VTG between experimental data and regression model for different orders of VTG and VJG for a p-channel G4FET (Device 4). .................................................... 82 Figure 4.58: Comparison of rout - VDS between TCAD data and regression model for different orders of VDS and VBG for an n-channel G4FET (Device 1). ................................................. 82 Figure 4.59: (a) Output from SPICE simulator, (b) experimental result. ..................................... 84 xvii Figure 4.60: Schematic of high voltage G4FET differential amplifier (Q 1,2: 0.3 µm ×10/2.4 µm, VJG = 0 V, VBG =0 V; Q 3,4: 0.35 µm ×2 /10 µm, VJG = 0 V, VBG = 0 V; Q 5,6: 0.3 µm×10/2.4 µm, VJG =VDD, VBG = 0 V). ................................................................................................... 85 Figure 4.61: Output of G4FET Differential amplifier (0.97 Vp-p compared to experimental value of 1 Vp-p) in non-inverting unity gain configuration (VDD = 10 V, Vin = 1 Vp-p square wave with 6 V offset). .................................................................................................................... 86 Figure 4.62: Comparison between isolines of test data and linear spline model (Device 1) for different junction-gate voltages ranging from -4 V to 0 V in 1 V increment. ...................... 90 Figure 4.63: Comparison between isolines of test data and cubic spline model (Device 1) for different junction-gate voltages ranging from -4 V to 0 V in 1 V increment. ...................... 91 Figure 4.64: Comparison between isolines of test data and linear spline model (Device 2) and relative error for varying bottom-gate voltages from -4V to 4V in 2V increment arranged from bottom to top. ........................................................................................................................ 92 Figure 4.65: Comparison between isolines of test data and cubic spline model (Device 2) and relative error for varying bottom-gate voltages from -4 V to 4 V in 2 V increment arranged from bottom to top. ............................................................................................................... 93 Figure 4.66: Comparison of ISD - VSD between TCAD test data and linear spline model (Device 3) for different junction-gate voltages ranging from 0 V to 4 V. .............................................. 94 Figure 4.67: Comparison of ISD - VSD between TCAD test data and cubic spline model (Device 3) for different junction-gate voltages ranging from 0 V to 4 V. .............................................. 94 Figure 4.68: Comparison between test data and linear spline model isolines (Device 4) for variation in junction-gate voltages from 0.2 V to 1.8 V in 0.4 V increment arranged from top to bottom. ............................................................................................................................................... 95 xviii Figure 4.69: Comparison between test data and cubic spline model isolines (Device 4) for variation in junction-gate voltages from 0.2 V to 1.8 V in 0.4 V increment arranged from top to bottom. ............................................................................................................................................... 96 Figure 4.70: Comparison between TCAD data and cubic spline model of isolines for different widths ranging from 0.3 to 0.5 µm in .05 µm increment arranged from bottom to top. ....... 97 Figure 4.71: Comparison of gm – VTG between TCAD data and cubic spline model for an n-channel G4FET (Device 1). ................................................................................................................ 98 Figure 4.72: Comparison of rout – VDS between TCAD data and cubic spline model for an n- channel G4FET (Device 1). ................................................................................................... 98 Figure 4.73: Behavioral model of an n-channel G4FET for spline interpolation......................... 99 Figure 4.74(a) Output from circuit simulator (b) Experimental result. ...................................... 100 Figure 4.75: Output of amplifier (1.03 Vp-p compared to experimental value of 1 Vp-p) in non- inverting unity gain configuration (VDD = 10 V, Vin = 1 Vp-p square wave with 6 V offset). ............................................................................................................................................. 101 Figure 4.76: Configuration 1 of analog multiplier using G4FET. ............................................... 103 Figure 4.77: Configuration 2 of analog multiplier using G4FET. ............................................... 103 Figure 4.78: DC transfer characteristics for configuration 1 (W = 0.35 µm, L = 10 µm, VDD = 10 V, Ibias = 15 µA, Vbias1 = 1.7 V, Vbias2 = -1.8 V, RL = 500 kΩ); (a) measurement results reproduced from [37], (b) simulation results using cubic spline model. ............................ 104 Figure 4.79: DC transfer characteristics for configuration 2 (W = 0.35 µm, L = 5 µm, VDD = 5 V, Ibias = 10 µA, Vbias1 = 0 V, Vbias2 = -3 V, RL = 500 kΩ); (a) measurement results reproduced from [37], (b) simulation results using cubic spline model. ............................................... 105 xix Figure 4.80: Product of a 20 Hz, 1 Vp-p sinusoidal-wave with 500 Hz, 1 Vp-p square-wave (W = 0.3 µm x 10, L = 2.4 µm, VDD = 3.5 V, VSS = -3.5 V, Ibias = 35 µA, Vbias1 = 2 V, Vbias2 = -2.5 V, RL = 100 kΩ); (a) measurement results, (b) simulation results using cubic spline model. ...... 107 Figure 4.81: Product of a 10 Hz, 4 Vp-p triangular-wave with 200 Hz, 4 Vp-p square-wave (W = 0.35 µm, L = 5 µm, VDD = 5 V, Ibias = 15 µA, Vbias1 = 0 V, Vbias2 = -3.5 V, RL = 200 kΩ); (a) measurement results, (b) simulation results using cubic spline model. .............................. 108 Figure 5.1: Output of NDR LC oscillator; (a) measurement result, (b) simulation result. ......... 114 Figure 5.2: Amplitude Modulated(AM) signal; (a) measurement result, (b) simulation result. . 115 Figure 5.3: High voltage differential amplifier output from the macromodel simulation. ......... 116 Figure 5.4: DC transfer characteristics for configuration 1 (W = 0.35 µm, L = 10 µm, VDD = 10 V, Ibias = 15 µA, Vbias1 = 1.7 V, Vbias2 = -1.8 V, RL = 500 kΩ); (a) measurement results reproduced from [7], (b) simulation results using the macromodel. ...................................................... 117 Figure 5.5: DC transfer characteristics for configuration 2 (W = 0.35 µm, L = 5 µm, VDD = 5 V, Ibias = 10 µA, Vbias1 = 0 V, Vbias2 = -3 V, RL = 500 kΩ); (a) measurement results reproduced from [7], (b) simulation results using the macromodel. ...................................................... 118 Figure 5.6: Product of a 20 Hz, 1 Vp-p sinusoidal-wave with 500 Hz, 1Vp-p square-wave (W = 0.3 µm x 10, L = 2.4 µm, VDD = 3.5 V, VSS = -3.5 V, Ibias = 35 µA, Vbias1 = 2 V, Vbias2 = -2.5 V, RL = 100 kΩ); (a) measurement results, (b) simulation results using the macromodel. .......... 120 Figure 5.7: Product of a 10 Hz, 4 Vp-p triangular-wave with 200 Hz, 4 Vp-p square-wave (W = 0.35 µm, L = 5 µm, VDD = 5 V, Ibias = 15 µA, Vbias1 = 0 V, Vbias2 = -3.5 V, RL = 200 kΩ); (a) measurement results, (b) simulation results using the macromodel. .................................. 121 Figure 5.8: Schematic of a multi-threshold Inverter. .................................................................. 123 Figure 5.9: Output of a multi-threshold inverter. ........................................................................ 123 xx Figure 5.10: Symbol of a G4FET programmable gate. ............................................................... 124 Figure 5.11: Output of a programmable gate. ............................................................................. 125 Figure 5.12: Schematic of the G4FET full adder. ....................................................................... 125 Figure 5.13: Output from the full adder. ..................................................................................... 126 Figure 6.1: Schematic of the cross-section of a G4FET in depletion all around operation......... 129 Figure 6.2: Comparison between test data and model for different junction-gate voltages, with both the top-gate and the bottom-gate biased at 0 V. .................................................................. 132 Figure 6.3: Comparison between test data and model for different junction-gate voltages, with the top-gate and the bottom-gate biased at 0 V and -3 V, respectively. ................................... 132 Figure 6.4: Comparison between test data and model for different top-gate voltages, with the junction-gate and the bottom-gate biased at 0 V and -3 V, respectively. ........................... 133 Figure 6.5: Comparison between test data and model for different top-gate voltages, with the junction-gate and the bottom-gate biased at -1.5 V and -3 V respectively. ........................ 133 Figure 6.6: Comparison between test data and model for different bottom-gate voltages, with both the junction-gate and the top-gate biased at 0 V. ................................................................ 134 Figure 6.7: Comparison between isolines of test data and model for different junction-gate voltages, with the top-gate and the bottom-gate biased at 2.5 V and 0 V, respectively. .... 137 Figure 6.8: Comparison between isolines of test data and model for different junction-gate voltages, with the top-gate and the bottom-gate biased at 3 V and 0 V, respectively. ....... 137 Figure 6.9: Comparison between isolines of test data and model for different junction-gate voltages, with the top-gate and the bottom-gate biased at 3.5 V and 0 V, respectively. .... 138 Figure 6.10: Comparison between isolines of test data and model for different junction-gate voltages, with the top-gate and the bottom-gate biased at 4 V and 0 V, respectively. ....... 138 xxi Figure 6.11: Comparison between isolines of test data and model for different junction-gate voltages, with the top-gate and the bottom-gate biased at 4.5 V and 0 V, respectively. .... 139 1 Chapter 1 – Introduction 1.1 Motivation Transistor is the key active component in practically all modern electronics and it is considered as one of the greatest technological inventions of the 20th century [1]. The ability to be mass-produced using a highly automated process resulting in a very low per-transistor cost has cemented its supreme role in the modern world. The invention of the first transistor at Bell Laboratories was named an IEEE Milestone in 2009 [2]. Although the first patent of a field-effect transistor was filed in 1926 [3], the real world transistor revolution actually started with the invention of bipolar junction transistor in 1948 which revolutionized the field of electronics by a rapid replacement of vacuum tubes as active elements in electronic devices. In contrast to the bulky, unreliable and excessive power consuming electronic circuits made with vacuum tubes, transistors provided a low-power, lightweight, faster and reliable alternative. Although over a billion discrete transistors are produced every year [4], the vast majority of transistors are now produced in integrated circuits introduced in 1958 independently by Jack St. Clair Kilby [5] and Robert Norton Noyce [6]. The amazing technological advancements in the semiconductor industries have been dictated by the desire to achieve Moore’s law [7]. In 1965, Gordon Moore stated that the number of transistors in integrated circuit (IC) would double every year which he later, in 1975, revised as a doubling in every two years. Moore’s law has been the main driving factor during the last 50 years for the enhancement of device performances primarily through smaller feature size and larger chips. The cost per transistor and the switching power 2 consumption per transistor went down, while the memory capacity and speed went up. Over the years, transistor sizes have decreased from tens of microns in the early 1970s to 10 nanometers in 2017 [8] with a corresponding million-fold increase in transistors per unit area as shown in Figure 1.1. The vast majority of applications now has bulk silicon device as the active element in VLSI (very large scale integration) and ULSI (ultra large scale integration) circuits. Figure 1.1: Moore’s Law dictating transistor counts in microprocessor over the years [9]. However, bulk silicon devices are now faced with some fundamental physical limits. Some of the non-idealities such as subthreshold conduction, gate oxide leakage and reverse-biased junction leakage can no longer be ignored since they can potentially consume more than half of the total power in modern high-performance VLSI chips [10]. The increase in doping concentration has reduced carrier mobility due to impurity scattering resulting in transconductance degradation. With the increased proximity of drain and source electrodes, drain has started to play 3 a vital role in channel formation causing the threshold voltage roll-off due to DIBL (drain induced barrier lowering) and a decrease in output resistance affecting analog circuit design. The scaling of switching time has slowed down since the interconnect capacitance has started to become a larger portion of total capacitance. With the very thin gate oxide of today, the leakage from quantum mechanical tunneling is increasing the power consumption and adversely affecting transistor operation. These problems are making conventional scaling less feasible as can be observed from the change of direction in ITRS road map from 2013 to 2015 in Figure 1.2. Figure 1.2: Change of direction in gate length scaling from 2013 to 2015 ITRS report [13]. Researchers have been looking for new process technologies which can solve the problems associated with bulk silicon scaling and enable the semiconductor industry to extend Moore’s law in the foreseeable future as shown in Figure 1.3. A promising candidate is silicon-on-insulator (SOI) technology with its long list of reported advantages[11]. It has a lower parasitic capacitance due to isolation from the bulk silicon resulting in lower power consumption at matched performance. SOI transistors have shown reduced short channel effect, better subthreshold swing 4 and the ability to handle higher voltage and higher temperature, compared to bulk CMOS [12]. Lower leakage currents due to isolation increases the power efficiency. It has a lower temperature dependence and is suitable for radiation hardened application with the need for reduced redundancy. It prevents latch-up by the complete isolation of the n- and p-well structures and enables implementation with a smaller chip area. Major companies, including IBM, AMD and Freescale, began manufacturing microprocessors using SOI substrates in the early 2000’s heralding its entrance into the mainstream semiconductor industry. Figure 1.3: Possible alternatives for extending Moore’s law [13]. In SOI technology, each transistor can have more than one gate. Experiments with different variations in gate configuration have been done and have resulted in a wide array of multi-gate transistors [14] such as wrapped-gate transistor, “double-gate transistor, “FinFET, ‘tri(ple)-gate transistors’, ‘gate-all-around transistors’ etc. However, the number of independent gates can be extended to four in SOI technology and it was named MOSJFET [15] or four gate field effect transistor (G4FET) [16] . G4FET retains the advantages of SOI technology and offers exciting new opportunities for analog and mixed-signal applications, quaternary logic functions and electrostatically formed nanowire with superior conduction properties. 5 The widespread use of a technology in circuit design is heavily dependent upon good SPICE models for CAD tools which are now ubiquitous in circuit design. Sophisticated models for existing transistors integrated with CAD tools have enabled designers worldwide to design excellent circuits which are in a large part responsible for the technology boom of the last 50 years. Since G4FET is a relatively new technology, a fast, robust and accurate SPICE model is absolutely necessary for aiding circuit designers to transform G4FET into a mainstream technology. 1.2 Research Goal The goal of this research effort is to develop robust, accurate and efficient SPICE model for G4FET and implement it as a circuit building block in commercial simulators. The existence of four independent gates makes this modeling work particularly challenging. In this work, four different numerical models have been developed and implemented in commercial circuit simulator, each with its own pros and cons. The results have been compared with both TCAD Sentaurus from Synopsys® and with experimental results. In addition, a macromodel is developed combining already existing SPICE models of MOSFET and JFET. Moreover, two physics-based compact modeling approaches have also been adopted to model particularly useful conduction mechanisms. The research goal can be summarized as developing the following models: 1. Development and CAD implementation of four numerical models: A. Multivariate Lagrange interpolation polynomial model, B. Multidimensional Bernstein polynomial model, C. Multivariate regression polynomial model, 6 D. Multidimensional spline interpolation model. 2. Development of a macromodel combining existing JFET and MOSFET models. 3. Development of a physics-based compact model. 1.3 Dissertation Overview This dissertation is divided into seven chapters. The limitation of bulk-CMOS technology and the need for multi-gate SOI technology are explained in Chapter 1. The evolution of G4FET and the necessity of suitable SPICE models are also discussed in Chapter 1. Previous analytical and modeling works on G4FET and other transistors are discussed in Chapter 2. The device structure and operating mechanism of G4FET are discussed in Chapter 3. The methodology and results of four numerical modeling approaches (Lagrange, Bernstein, Regression and Spline) are discussed in Chapter 4. The macromodel of G4FET combining existing transistor models is explored in Chapter 5. Two physics-based modeling approaches for SPICE implantation are discussed in Chapter 6. Conclusions and future works are summarized in Chapter 7. 7 Chapter 2 - Literature Review 2.1 Previous Works on G4FET G4FET, a relatively new member in the SOI multi-gate device family, was first reported in 2002 [15]. This unique SOI transistor combines MOSFET and JFET transistor actions in a single silicon body. Due to this combination of MOSFET and JFET functionality, this transistor was called a MOSJFET [15]. It was also named G4FET [16] since it has four independent functional gates. Extraction methods for threshold voltage, mobility and subthreshold swing in the linear region were demonstrated in [17]. The experimental results from a partially-depleted (PD)-SOI G4FET showed the dependence of these parameters on different gate biases. In addition to the experimental results, numerical simulation is important for understanding the several conduction mechanisms inside the transistor and 3-D simulations were performed to shed light on the role of multiple gates [18]. A non-uniform doping profile was used to reproduce the channel characteristics of fabricated devices. In [19], various operation modes of G4FETs were analyzed based on measured current- voltage, transconductance and threshold characteristics. The optimization of important device parameters such as threshold voltage, subthreshold swing, mobility using particular combination of gate biasing was also shown. Volume and interface conduction mechanism were clarified using numerical simulation. The unique ability of switching using any of its four independent gates was also discussed. 8 The charge coupling between front, back and lateral junction-gates was considered and a 2-D analytical relationship for the fully-depleted body potential was derived in [20]. This work was extended in [21] and a closed form front-interface threshold voltage expression was derived as a function of the back and the lateral gate voltages for different back interface conditions such as accumulation, depletion and inversion. The subthreshold operating region of G4FET was explored in [22] and it showed better subthreshold swing compared to conventional bulk MOSFET. There is a flexibility of adjusting the subthreshold slope of MOS gates or junction-gates using the remaining gate biases. A very interesting application of G4FET is the formation of quantum wire. The quantum wire can be electrostatically formed when the conducting channel is surrounded by depletion regions induced by vertical MOS and lateral JFET gates [23]. In this unique conduction mechanism named depletion-all-around (DAA), majority carriers flow in the volume of the silicon film far from the silicon/oxide interfaces. The control of lateral gates on the conduction channel can be adjusted by changing biases on the vertical gates. There is a reduced sensitivity of the channel to the oxide and interface defects, low subthreshold swing, high gm/ID ratio, high mobility, low noise, and high immunity to ionizing radiation [24]. The fully-depleted version of the G4FET was introduced and its characteristics were systematically investigated in [25]. This work demonstrates that the thinning-down of the silicon film enhances vertical coupling between the front and the back gates and reduces the horizontal coupling between the lateral gates. As a consequence, the direct influence of the lateral junction- gates on the body potential distribution is reduced. The operation and performance of G4FET was presented from the low voltage to the high voltage regime [26]. Devices fabricated in 0.35 µm 3.3 V partially-depleted SOI process are shown 9 to have a breakdown voltage of 15 V, excellent subthreshold swing, and high mobility. Low- frequency noise characteristics of G4FET were reported in [27]. A comparison of noise power spectral density between surface and volume conduction was presented and its dependence on biasing conditions was explored. A charge sheet model has been recently proposed to analyze the transistor characteristics of fully-depleted G4FETs [28]. Here, surface accumulation behavior, drain current and gate capacitance of fully-depleted G4FET are modeled analytically. In [29], a mathematical model is developed to determine the subthreshold swing of thin- film fully-depleted G4FET. A mathematical model of potential distribution has been derived considering three dimensions of a fully-depleted p-channel G4FET in [30]. A physics-based mathematical model is proposed in [31] to determine the accumulation layer thickness in thin film fully depleted G4FETs. Another mathematical model is developed in [32] to determine the 3-D potential distribution of a fully-depleted G4FET. Based on the exact solution of the Poisson equation, a new two-dimensional model of potential and threshold voltage for the fully-depleted G4FET was developed in [33]. Several innovative analog and digital circuit applications of G4FET have been reported over the years. A complementary pair of G4FETs can exhibit negative differential resistance (NDR) due to the JFET functionality of its lateral gates. LC oscillator and Schmitt trigger circuits were experimentally demonstrated using G4FET NDR device [34]. G4FETs can operate under higher voltages compared to bulk silicon MOSFET counterparts using the same process technology. High voltage current mirror and differential amplifier based on G4FET were experimentally demonstrated in [35]. The four gates of G4FETs can be utilized to make innovative circuits with reduced transistor count. A novel four quadrant analog multiplier topology was demonstrated in [36] with 10 only four transistors at its core. Two different configurations, using different combination of gate inputs are shown. A G4FET based temperature-compensated voltage reference circuit, without the use of the standard bandgap architecture, was demonstrated using standard 3.3 V/ 0.35 µm partially-depleted PD-SOI process [37]. In the arena of digital circuits, the independent multi-gate functionality helps reduce the transistor count per logic function and enhances design flexibility. Novel G4FET based logic- circuits such as adjustable-threshold inverter, real-time reconfigurable logic gates and DRAM cell were experimentally demonstrated [38]. In [39], the G4FET was demonstrated as a universal and programmable logic gate that can lead to the design of more efficient logic circuits. A new full adder design based on the G4FET utilizing only three transistors and two inverters is proposed. The operation of the G4FET can be interpreted as a complex four-input switching process and can be used for the computation of multiple-input threshold logic functions using a single device. Leveraging these unique capabilities a novel threshold logic family capable of efficient computation of complex logic functions was reported recently [40]. 2.2 Previous Works on Numerical Modeling Numerical models offer an alternative to the physics-based analytical models for rapid, accurate device modeling. The approach is to develop a methodology which takes measured or simulated data as input and then based on these empirical results, accurately reproduces the complex nonlinear behavior of the semiconductor devices. In most cases, they are equally applicable to different types of transistors such as MOSFET, MESFET, HEMT, DGFET etc. fabricated using various process technologies. 11 The most commonly used methods utilize look-up table and quadratic or higher order polynomials for interpolation between data points. The authors in [41] use a table-based approach for the empirical modeling of FETs in circuit simulators to address the specific requirements of analog circuit design, such as accuracy in reproducing small-signal parameters, large signal nonlinearities, subthreshold characteristics, substrate effects, short-channel effects, and voltage dependent capacitances. A table lookup model for MOSFETs consisting of a main table and a coarse 3-D sub-table to incorporate substrate effects. and a table to interpolate between channel length was implemented in SPICE 3 to overcome the inadequacies of analytical models in representing short channel effects [42]. An approach to dynamic MOSFET modeling, which is especially suited for the simulation of low-voltage mixed signal circuits was reported [43]. The model is based on the interpolation of terminal charges and conductive currents with physically motivated functions such as piecewise polynomial and/or exponential splines based on transient current/voltage data obtained through measurement or simulation of the devices. A general n-dimensional first order continuous table model was proposed in [44]. Each table model was shown to reproduce the exact behavior of the DC current expressions of two basic physical device models; the Ebers-Moll bipolar transistor model and the GLASMOST MOSFET model with high accuracy and less evaluation times than advanced physical CAD device models. Authors in [45] developed simple interpolation methods to construct any current table from a small basis set of tables for variation of width, length and temperature. Quadratic B-splines with not-a-knot boundary conditions were used for length and temperature interpolation, whereas simple scaling along with decomposition of channel was done for width variation to take narrow width non-idealities into consideration. 12 The table lookup approach was first applied for simulation of digital circuits in the timing simulator MOTIS [46], which has been developed at Bell Laboratories in 1975. The timing simulator provides timing information on the propagation of signals through MOS digital circuits. A blending function combining exponential and polynomial interpolation for the accurate evaluation of the MOSFET drain current in the transition region between weak and strong inversions was implemented in [47]. This model offers several interpolation methods in the table model providing the model user with a flexibility to choose based on the required simulation speed, memory consumption and accuracy. Implementation of the model in circuit simulation showed good results in DC, transient, and AC analyses. Table data has also been used to model devices for RF simulation [48]. In this model, the device characteristics of GaAs FET devices are determined by state functions which define nonlinear relationships for the 3-terminal lumped elements. An array of s-parameters, measured over a wide range gate and drain biases, is used to determine these state functions. Good prediction of high-order harmonics has made this model suitable for RF simulations. In [49], this Bernstein approximation technique is extended to multidimensional variation diminishing interpolation and applied to DC current and intrinsic charge modeling of the MOSFET to increase simulation efficiency. Information about device operating point is extracted by functional reconstruction from stored data during transient simulation. The formulation of the numerical model preserves continuity and monotonicity facilitating the convergence in Newton- Raphson algorithm for solving the differential circuit equations. Monotonic Piecewise Cubic Interpolation was used in [50] to determine the MOSFET operating point using stored table value generated by a 2-D device simulator. In [51], the quadratic fits were used to model triode region whereas linear fits were used for the saturation region. 13 However, it resulted in a discontinuity in the device conductance during the transition from triode to saturation region. Authors in [52] used a tableau-style spline formulation using quadratic splines ensuring continuity of the function and its derivative and presented a new data-compression scheme for polynomial spline coefficient storage. The splines were optimized to reduce the number of segments and preserve the monotonicity of the model equations. A three dimensional table lookup MOSFET model was presented in [53] showing good accuracy and short computation time. A conversion table was adopted for logarithmic operation to capture the weak inversion effect with log-linear characteristics. In another work on table method [54], a methodology of generating compact and accurate first order table model for highly nonlinear multidimensional behavior was demonstrated. 2.3 Previous Works on Macromodels The number of elements in today’s integrated circuit can range from several dozens to hundreds of millions. If each individual element is modeled separately, the simulation run time will be prohibitively long. Macromodels are used to simplify circuits in a way so that the desired behavioral characteristics remain the same for all practical purposes while the computational time gets substantially reduced. Important circuit blocks like operational amplifiers and comparators are usually employed in simulators using their macromodels. The need for macromodel in IC subsystem design is discussed in [55]. The authors in [56] developed a macromodel for integrated circuit (IC) operational amplifiers (op amp) with an excellent pin-for-pin representation. The model uses 14 common elements available in most circuit simulators. This macromodel is a factor of more than six times less complex, an order of magnitude faster and less costly compared to op amp models at the electronic device level. Logic simulation and macromodels have also been developed for digital logic blocks ([57], [58]). A behavioral multiport macromodel for the input buffers of digital integrated circuits is presented in [59] which offers comparable accuracy and improved efficiency compared to the transistor-level models. A macromodel for integrated-circuit comparators, capable of providing up to an order of magnitude reduction in CPU time and matrix size for CAD, was reported in [60]. A lumped parameter macromodel was derived from transistor characterization data to use in SPICE analyses for predicting the single-event upset thresholds for Texas Instruments SIMOX( Separation by IMplantation of OXygen) SOI SRAMs [61]. Physico-chemical model of the ISFET (ion-sensitive field-effect transistor) was developed in [62] using a behavioral macromodel that can be used in commercial SPICE programs. The proposed macromodel was shown to operate satisfactorily even under subthreshold conditions. The main goal was to get rid of the drawbacks associated with developing built-in models such as the availability of the program source, a deep knowledge of the code subroutines and structure, and the requirement of compiling the entire program for a new model implementation. An empirical macromodel for a p-channel floating-gate MOS synapse transistor simulation consisting of a transistor and controlled sources was proposed in [63]. The model did not use the channel potential in its description enabling its application in any SPICE circuit simulator. In [64], an improved SPICE macro-model for the LDMOS (laterally diffused MOS) device was proposed with better performance compared to existing BSIM3 models in both DC and AC regions. Verilog-A modules consisting of standard elements make this model simulator 15 independent. The model used an adapted JFET to model the drift region resistance and shorted PMOS transistors for modeling the capacitance behavior of the drift region. SPICE macro- modeling techniques have also been used in [65] for the compact simulation of single electron circuits. 2.4 Previous Works on Physics-based Compact Modeling A number of works have been performed over the years on physics-based modeling of transistors. Gummel in [66] developed a model based on finite difference method for solving the model equations to provide information about internal parameters such as potential and electric field distribution along with terminal characteristics. This approach was modified in [67] using a new discretization technique for ensuring convergence. Building upon Scharfetter-Gummel algorithm, Slotboom [68] proposed a new model using two new artificial variables for linearization of the differential equations facilitating implementation in CAD programs. Early pioneers Pao and Sah came up with the classic double integral drain current expression and explored different characteristics of the transistor action [69, 70]. However, these formulas are computation intensive and CAD implementation required a simplified model. Brews in [71] proposed a charge sheet model which compresses the inversion layer into a conducting plane of zero thickness. With the scaling down of MOSFET, it gradually became apparent that in addition to linear and saturation regions, a third region of operation, namely, subthreshold conduction could no longer be ignored especially for low-leakage circuits. The subthreshold region is usually defined as the intermediate region between weak and strong inversion, where weak inversion starts when 16 the minority and the majority carrier concentrations at the surface are equal and the onset of strong inversion, typically known as threshold, occurs when the minority carrier concentration at the surface is equal to the majority carrier concentration in the bulk semiconductor. In [72], authors reconsidered the basic charge relationships to give a new formulation of the theory of the device for model characterization in a more general manner, and with greater accuracy than previously achieved. The contribution of the mobile channel charge to the silicon surface potential was taken into account and the model covered from sub-threshold to strong inversion conduction. In [73], the effect of drain voltage on the subthreshold operation as the channel length becomes shorter, the effect of substrate bias on both the shift in and the slope of the subthreshold curves, and the effect of temperature on the subthreshold current characteristics are discussed and incorporated into a one-dimensional model. In [74], the dependence of channel current in subthreshold operation upon drain, gate, and substrate voltages is formulated in another model. It also points out the fact that two-dimensional effects can cause dramatic increases in the drain conductance. In [75], an analytical model was presented for unifying the existing models for both short and long channel MOSFETs. Methods and results of a three-dimensional numerical model of small geometry MOSFETs were reported in [76]. The necessity of three-dimensional simulation as opposed to two- dimensional calculations is discussed and size effects in short and narrow channel enhancement and depletion FETs are analyzed. In [77], two-dimensional simulations were used to determine the relationship between the drain-induced barrier lowering and the punchthrough and a quasi one- dimensional Poisson equation was solved to find the onset voltage of the punchthrough . Also, a semi-empirical model, MOS3, was developed and installed into the circuit simulation program SPICE2.G. 17 Initially MOSFETs were not the first choice for analog circuit design. However, during the 70’s, improved noise performance, device matching, and frequency response have resulted in analog MOSFET circuits with performance comparable to or better than that of bipolar counterparts. This required a better small signal model for CAD implementation and the authors in [78] presented a first-order and a second-order large signal MOSFET models and derived corresponding small signal models. The small-signal model parameters are related to operating- point bias and the IC process used to fabricate the devices. The SPICE2 program provided three built-in MOS transistor models, known as the first generation models [79]. The first one is the Level-1 model with its fairly simple expressions similar to the often used square law current equation and is suitable for preliminary analysis. This is mostly based on the works of Shichman and Hodges [80].The Level-2 model dived deeper into detailed device physics but still had some problems with small geometry transistors and convergence issues. The Level-3 model was an attempt to merge physics-based approach with empirical parameter fitting and started the semi-empirical modeling approach for reproducing device characteristics. The authors in [81] developed the now famous ‘Berkeley Short-channel IGFET Model (BSIM)’ based upon AT&T Bell Laboratories’ CSIM (Compact Short-channel IGFET Model) with substantial enhancements [82]. This was the beginning of the second generation of SPICE models. Among the factors influencing conduction, mobility and recombination-generation need to modeled appropriately for faithful reproduction of experimental data. The dependence of carrier mobility on electric field, temperature and doping density has been analyzed by different authors. In [83], Canali et al. presented experimental data for electron and hole drift velocity in silicon for 18 high electric fields up to 6×104 V/cm and wide temperature range from 300 to 430 K and proposed an analytical expression based on curve fitting to describe the experimental data. An analytical expression of electron and hole mobilities in silicon based on experimental data was reported in [84] which is valid for wide range of temperature and doping concentration. A concentration dependent mobility expression for different dopant materials such as boron, phosphorus and arsenic in silicon was proposed in [85]. A unified model known as ‘University of Bologna mobility model’ was proposed by Reggiani [86, 87] incorporating dependences on doping, temperature and electric field. The carrier generation and recombination depend on temperature and carrier density. Hall [88] and Shockley-Read [89] independently established a universal expression for carrier- recombination and generation. The dependence of carrier lifetime, the most important parameter for determining the rate of recombination-generation, on temperature and electric field was analyzed in [90]. With the advent of silicon-on-insulator (SOI), new compact models exploring different flavors of this new technology were reported. In [91], a physics-based SPICE model called BSIMPD is developed for application of partially-depleted SOI technologies in deep-submicron CMOS designs. The model was developed on top of the industry-standard bulk-MOSFET model BSIM3v3 ensuring scalability and robustness while capturing SOI-specific dynamic behaviors such as built-in floating body, self-heating and body-contact models. Depending on dimension and bias, SOI MOSFET may operate in different modes i.e. body- contacted mode, partially depleted mode and fully depleted mode. A model has to incorporate a smooth transition between the modes of operation. The authors in [92] describe a unified framework to model the floating-body effects of various SOI MOSFET operation modes. 19 A surface-potential based multi-gate FET (MG-FET) compact model called BSIM-MG was reported in [93] for mixed-signal design applications. This model included effect of finite body doping on the electrical behavior of MGFETs and used a field penetration length model for short channel effects. It also included several physical effects such as poly-depletion effect and quantum-mechanical effect (QME). The continuity of terminal currents and charges was ensured for mixed-signal design. The authors also reported a similar BSIMIMG model for independent multi-gate operation in [94]. A process/physics-based compact model for non-classical MOSFETs having ultra-thin Si bodies (UTB) is discussed in [95]. The discussed model is essentially a compact Poisson– Schrodinger solver, including short-channel effects, and can be used for modeling nanoscale FD- SOI MOSFETs and generic double-gate (DG) devices. An analytic potential compact model was developed for symmetric DG MOSFETs without the charge sheet approximation to account for the “volume inversion” [96, 97]. A similar model has been developed for surrounding-gate (SG) MOSFETs [98]. Based on these works, a unified analytic drain–current model is presented for various kinds of multiple-gate (MG) MOSFETs, including quadruple-gate (QG), triple-gate (TG), Π-gate, and Ω-gate MOSFETs in [99]. Recently, surface potential based modeling, namely SP and PSP models have gained prominence for accurate modeling of scaled down transistors. In [100], a symmetric linearization method was reported for developing a core compact model of certain multiple-gate transistors without charge-sheet approximation resulting in a form very similar to a standard PSP MOSFET model. Authors in [101] reported a surface potential based approach for modeling partially- depleted (PD) SOI MOSFET. This model retains the physics-based formulation and scalability of 20 standard PSP while capturing SOI specific effects by including floating body simulation capability, parasitic body currents and capacitances. It also included a body resistance for accurate characterization and simulation of body-contacted SOI devices. A complete surface-potential- based compact model of dynamically depleted (DD) SOI MOSFETs was presented in [102]. EKV( Enz Krummenacher Vittoz) approach of device modeling [103] has also become popular over the years, especially for analog circuit design. In [104], a design oriented charge- based model based on EKV formalism for undoped DG MOSFETs under symmetrical operation was presented. 21 Chapter 3 - Device Structure and Operating Mechanism of G4FET 3.1 Multiple Independent Gate Silicon-On-Insulator (SOI) Transistor G4FET is a multiple independent gate transistor fabricated in silicon-on-insulator (SOI) technology. In this technology, a layered silicon-insulator-silicon substrate is used in place of a conventional bulk silicon substrate. The addition of silicon dioxide as the insulator just above the substrate and below the top silicon layer provides better isolation, prevents latch-up and reduces parasitic capacitance. This oxide layer is called the buried oxide (BOX). The topmost thin film of silicon on top of the buried oxide is the active region where all devices are fabricated. This is called epi/top Si layer. The bottom thick silicon layer is called the substrate or handle wafer. Figure 3.1 shows the layers of the SOI wafer. Si substrate Buried oxide Epi Si layer Figure 3.1: Three layers of SOI wafer. There are two types SOI wafers: 1) fully-depleted (FD) and 2) partially-depleted (PD) SOI. The difference lies in the thickness and the doping density of the top silicon layer. The film 22 thickness and the doping concentration in FDSOI is such that the film gets fully depleted without any biasing just due to work function difference, as shown in Figure 3.2. Silicon substrate BOX GOX Fully-depleted Silicon epi layer p + /n + p + /n + Poly Silicon Gate Figure 3.2: Cross-sectional schematic of a fully-depleted (FD) SOI device. On the other hand, PDSOI has a slightly thicker Si film compared to FDSOI. Thus the epi silicon layer does not get fully depleted and there is a neutral region with mobile charge carriers at the center of the film as shown in Figure 3.3. Silicon substrate p + /n + p + /n + GOX Neutral regionDepleted region Poly Silicon Gate BOX Figure 3.3: Cross-sectional schematic of a partially-depleted (PD) SOI. Since the top-gate needs to support less depletion charge in FDSOI, it can trigger a rapid increase in inversion charges and provide a higher switching speed. The depletion charge is limited by the buried insulator layer and this reduction in depletion capacitance results in a substantial improvement of the subthreshold swing that can go down to the minimum theoretical value of 60 mV/decade for MOSFET at room temperature. The better subthreshold properties enable FD SOI 23 transistors to operate at lower gate bias with lower power consumption. Another short channel effect plaguing modern MOSFETs is threshold voltage roll off which is substantially reduced in FDSOI. However, PDSOI operates in an intermediate stage between the bulk and the FDSOI transistor. Its body is not fully depleted, but suitable biases applied at gate can deplete the entire body free of mobile carriers. In addition, PDSOI provides both volume and surface conduction. Therefore, depending on application, decision has to be made as to which one is more appropriate. 3.2 G4FET Device Structure G4FETs can be fabricated using standard partially or fully-depleted SOI (PD/FD-SOI) process. It has four independent gates for modulating channel conduction. There are two lateral junction-gates which act like JFET gates and two vertical oxide gates which act like MOS gates. This transistor has also been called MOSJFET [15] since it combines both metal-oxide- semiconductor field-effect transistor (MOSFET) and junction field-effect transistor (JFET) actions in a single silicon island. G4FET is a majority carrier device. A regular p-channel SOI MOSFET with two body contacts on the opposite sides of the channel works as a n-channel G4FET. The p+ doped source and drain of the MOSFET now function as lateral junction-gates. They are used like JFET gates to control the channel conduction width. The top oxide gate works like a classical MOS gate whereas the buried oxide along with the substrate biasing acts as a bottom-gate. These vertical gates are used to create the accumulation/depletion/inversion of free carriers in the silicon epi layer near the top and the bottom oxide interfaces. The body contacts are highly doped to make Ohmic contact with the channel and are used as the source and the drain for the n-channel G4FET. An 24 accumulation/depletion-mode n-channel G4FET is thus realized from an inversion-mode, p- channel MOSFET. Similarly, a p-channel G4FET can be constructed from a conventional SOI n- channel MOSFET. Figure 3.4 shows the 3-D schematic structure of an n-channel G4FET. The cross section and the top view of the device are shown in Fig 3.5(a) and Figure 3.5 (b), respectively. The channel length and the channel width of the SOI MOSFET become the channel width and the channel length of the G4FET, respectively. It is evident that no specialized fabrication procedure is necessary for this device. 3.3 Principle of Operation The existence of four independent gates provides a multitude of possible combinations of gate biases, each giving rise to a unique conduction mechanism. The vertical gates can be inverted/depleted/ accumulated whereas the junction-gates are reverse biased in varying degrees for controlling the width of conduction channel. The flow of the drain current is perpendicular to the conventional MOSFET current flow. There can be three conduction paths, namely, 1) top surface conduction near gate oxide interface, 2) bottom surface conduction near buried oxide interface and 3) volume conduction inside the body away from vertical oxide interfaces. Depending on various applications, the specific components can be turned on or off using appropriate gate biases. In most application, the top-gate is accumulated and the transistor works as an accumulation mode MOSFET with two junction-gates providing JFET like control on the conduction channel. However, it is also possible to operate the vertical gates in depletion/inversion and this particular conduction mechanism, named depletion all around (DAA) has been shown to have very promising characteristics [24]. 25 Buried Oxide Source (n+) Drain (n+) TG (Poly Gate) BG (Substrate) JG1 p+ GOX JG 2 p+ Figure 3.4: 3-D Schematic of a G4FET structure. p + n - BODY p + POLY Left Junction gate Right Junction gate Top Gate Bottom Gate BOX GOX FOX Drain Source L ef t J u n c ti o n G a te R ig h t J u n c ti o n G a te Body P o ly S i GOX FOX C h a n n el W id th C h a n n el L en g th (a) (b) Figure 3.5: G4FET structure: (a) cross section and (b) top view. 26 3.4 Effect of Gate Bias on Conduction Path Numerical simulation in TCAD Sentaurus is used to visually demonstrate the effects of different gate biases on the conduction path. A three dimensional n-channel G4FET structure is created using Sentaurus Structure Editor and simulated using Sentaurus Device. The cross section halfway along the channel length is used here to demonstrate the effect of lateral and vertical biases on conduction path. The channel conduction depends on the concentration of electrons inside the channel which is shifted by different gate biases. Here, VTG is the top-gate voltage, VBG is the bottom-gate voltage and VJG is the junction-gate voltage applied at both junction gates which are connected together. Figure 3.6 shows the electron concentration for keeping all the biases at 0 V. As the top- gate goes from 0 to -3 V, as shown in Figure 3.7, the conduction region gets vertically pushed down. Similar effect is shown for bottom-gate inversion in Figure 3.8 where the channel gets vertically pushed up as bottom-gate is biased at -3 V. Figure 3.9 shows the combined inversion effect of vertical gates when a narrow wire like conduction path is created at the center away from both oxide surfaces. Figure 3.10 shows the effect of lateral depletion with both junction-gate reverse biased at -1 V. The channel now becomes narrower as lateral region near junction-gates gets depleted of free carriers. Figure 3.11 shows the effect of accumulation at top-gate when VTG = 3 V is applied. A thin layer of high electron density is formed near the oxide surface. Figure 3.12 shows the case when both the top and the bottom-gates are accumulated. In these two cases, the transistor provides both surface and volume conduction. 27 Figure 3.6: Electron density in the top silicon film at VTG = 0 V, VBG = 0 V and VJG = 0 V. Figure 3.7: Electron density in the top silicon film at VTG = -3 V, VBG = 0 V, VJG = 0 V. Figure 3.8: Electron density in the top silicon film at VTG = 0 V VBG = -3 V VJG = 0 V. 28 Figure 3.9: Electron density in the top silicon film at VTG = -3 V, VBG = -3 V, VJG = 0 V. Figure 3.10: Electron density in the top silicon film at VTG = 0 V, VBG = 0 V and VJG = -1 V. Figure 3.11: Electron density in the top silicon film at VTG = 3 V, VBG = 0 V and VJG = 0 V. 29 Figure 3.12: Electron density in the silicon film at VTG = 3 V, VBG = 10 V and VJG = 0 V. 3.5 Chapter Summary This chapter describes the physical structure of a G4FET transistor and its formation from a conventional SOI MOSFET is outlined. The added flexibility of G4FET can be obtained without any significant modification in the conventional SOI technology. The multiple independent gates provide G4FET with several possible operating conditions which are explained with the aid of numerical simulation. 30 Chapter 4 - Numerical Modeling of G4FET 4.1 Overview Analytical models are important for understanding the underlying physics of the semiconductor devices. Nowadays, in the highly scaled down semiconductors, a number of physical phenomena, such as high-field mobility, carrier velocity saturation, gate oxide tunneling, drain induced barrier lowering and hot carrier effect dictate the semiconductor device characteristics. The physical phenomena are highly nonlinear in nature and their exact solution requires solving a set of coupled nonlinear differential equations, namely (i) Poisson, (ii) electron continuity and (iii) hole continuity equations. In today’s small dimensional structure, quantum mechanical effect also has to be taken into consideration requiring coupled solution of Schrodinger’s equation as well. G4FET configuration requires a 3-D solution which makes it much harder and more time consuming. A closed form analytical expression, even in piecewise form, becomes almost impossible without a number of approximations. Numerical modeling is another way of device modeling that gets rid of the above- mentioned problems. Different numerical methods have been explored over the years for modeling devices based on available data and are discussed in section 2.2. In this work, four different numerical models have been developed and implemented in commercial simulators for modeling G4FETs. These methods are: 1) multivariate Lagrange interpolation polynomial model, 2) multidimensional Bernstein polynomial model, 3) multivariate regression polynomial model and 4) multidimensional linear and cubic spline interpolation model and are described in the following sections. 31 4.2 Numerical Method 1 (Multivariate Lagrange Interpolation Polynomial Model) The first numerical model is the multivariate Lagrange interpolation polynomial which was proposed in [105]. Available data from TCAD simulation and experimental results have been used to develop numerical models for capturing the current-voltage (I-V) characteristic of a G4FET. Given a set of distinct points (xi,yi), there is a unique polynomial of the least degree which, at each point xi, provides the corresponding value yi. This interpolating polynomial can be evaluated using Lagrange polynomial, Neville’s algorithm or Newton polynomial. A single expression is derived for predicting the device characteristics over the entire region of device biasing inside the interpolation range. 4.2.1 Model Formulation The model formulation involves determining a polynomial for fitting a set of chosen data points. Both simulation and experimental results are used for obtaining these training data set. For this one-dimensional case, a polynomial f(x) of degree m is developed, such that, 𝑦𝑖 = 𝑓(𝑥𝑖) (4.1) for a chosen set of (m+1) data points (x0,y0),….(xi,yi),….,(xm,ym). Here, f(x) is the desired interpolation polynomial and the data points are called the node points for interpolation. The Lagrange interpolation polynomial is denoted by L(x) with degree m which satisfies the condition that L(xi) = yi for i = 0, 1, …, m. It can be written as a linear combination of basis polynomials, li(x) as, L(x) = ∑ 𝑙𝑖(𝑥)𝑦𝑖 𝑚 𝑖=0 (4.2) 32 where, the Lagrange basis polynomial li(x) is given by, 𝑙𝑖(𝑥) = (𝑥−𝑥0)(𝑥−𝑥1)…(𝑥−𝑥𝑖−1)(𝑥−𝑥𝑖+1)…(𝑥−𝑥𝑚) (𝑥𝑖−𝑥0)(𝑥𝑖−𝑥1)…(𝑥𝑖−𝑥𝑖−1)(𝑥𝑖−𝑥𝑖+1)…(𝑥𝑖−𝑥𝑚) = ∏ (𝑥−𝑥𝑗) (𝑥𝑖−𝑥𝑗) 𝑚 𝑗=0,𝑗≠𝑖 (4.3) The form of basis polynomial indicates that at each interpolating point x = xi, li(x) = 1 and all the other basis polynomials lj(x) = 0 (j ≠ 𝑖). Consequently, at each node point xi, L(xi) = yi, and error at node point becomes zero which is a very desirable property of Lagrange polynomial. The basis polynomial does not depend on the dependent variable. The Lagrange polynomial can be extended for two dimensional cases as follows, 𝐿(𝑥, 𝑦) = ∑ 𝑙𝑖(𝑥)(∑ 𝑙𝑗(𝑦)𝑓(𝑥𝑖, 𝑦𝑗)𝑗𝑖 ) (4.4) where, the basis polynomials li(x) and lj(y) are expressed as shown in Equation (4.3). This demonstrates that the Lagrange polynomial can be written in a recursive fashion. For more than two variables, the Lagrange polynomial can be expanded in the same manner as in Equation (4.4). For four independent variables, it can be written as, 𝐿(𝑢, 𝑣, 𝑤, 𝑥) = ∑ 𝑙𝑖(𝑢)(∑ 𝑙𝑗(𝑣)(∑ 𝑙𝑘(𝑤)(∑ 𝑙𝑙(𝑥)𝑓(𝑢, 𝑣, 𝑤, 𝑥))))𝑙𝑘𝑗𝑖 (4.5) If the variables (u, v, w and x) in equation (4.5) are replaced with VDS (drain-to-source voltage), VTS (top-gate-to-source voltage), VBS (bottom-gate-to-source voltage), and VJS (junction- gate-to-source voltage), the drain current can be expressed in the form of Lagrange polynomials as follows, 𝐼𝐷𝑆(𝑉𝐷𝑆, 𝑉𝑇𝑆, 𝑉𝐵𝑆, 𝑉𝐽𝑆) = ∑ 𝑙𝑖(𝑉𝐷𝑆)(∑ 𝑙𝑗(𝑉𝑇𝑆)(∑ 𝑙𝑘(𝑉𝐵𝑆)(∑ 𝑙𝑙(𝑉𝐽𝑆)𝑓(𝑉𝐷𝑆, 𝑉𝑇𝑆, 𝑉𝐵𝑆, 𝑉𝐽𝑆))))𝑙𝑘𝑗𝑖 (4.6) Interpolating polynomial is susceptible to Runge’s phenomenon i.e. oscillation, especially at the edges of an interval which increases in magnitude with polynomials of high degree over a set of equidistant interpolation points. The oscillation can be minimized by using nodes that are 33 distributed more densely towards the edges of the interval. One possible choice for generating non- uniform grid for this purpose is using Chebyshev nodes. For nth order interpolation between an arbitrary interval [a,b], Chebyshev node xi (i = 0,1,2,…,n) is defined as, 𝑥𝑖 = 1 2 (𝑎 + 𝑏) + 1 2 (𝑏 − 𝑎)cos ( 2𝑖−1 2𝑛 𝜋) (4.7) For the variable of the highest order, available data points closest to Chebyshev nodes have been used for the development of Lagrange model instead of a uniform node set. The order of the Lagrange polynomial is represented by the highest power of the independent variable and depends on the number of data points taken corresponding to that variable. If the order of an independent variable x is denoted by Ox and the number of sample points used for interpolation is nx then, 𝑂𝑥 = 𝑛𝑥 − 1 (4.8) In this work, polynomial models are used for at most four variable functions. If the order of the variables VDS, VTG, VBG, VJG are ODS, OTG, OBG and OJG, respectively, then the total number of terms (Nterms) in the final expression will be, 𝑁𝑡𝑒𝑟𝑚𝑠 = (𝑂𝐷𝑆 + 1)(𝑂𝑇𝐺 + 1)(𝑂𝐵𝐺 + 1)(𝑂𝐽𝐺 + 1) (4.9) The number of required additions and multiplications for evaluating the polynomial for a particular set of VDS, VTS, VBS, and VJS will dictate the speed of the circuit simulation. If the total number of additions/subtractions is Nadd and the total number of multiplications is Nmul then, 𝑁𝑎𝑑𝑑 = (𝑂𝐷𝑆 + 1)(𝑂𝑇𝐺 + 1)(𝑂𝐵𝐺 + 1)(𝑂𝐽𝐺 + 1) − 1 = 𝑁𝑡𝑒𝑟𝑚𝑠 − 1 (4.10) and 𝑁𝑚𝑢𝑙 = (𝑂𝐷𝑆+1)(𝑂𝑇𝐺+1)(𝑂𝐵𝐺+1)(𝑂𝐽𝐺+1)(𝑂𝐷𝑆+𝑂𝑇𝐺+𝑂𝐵𝐺+𝑂𝐽𝐺) 2 − 𝑁𝑎𝑑𝑑 (4.11) 34 which, after minor algebraic simplification becomes, Nmul = 𝑁𝑡𝑒𝑟𝑚𝑠 × ((∑ 𝑂𝑖 )𝑖=𝐷𝑆,𝑇𝐺,𝐵𝐺,𝐽𝐺 /2 -1) +1 (4.12) This dependence dictates that the complexity of the model will increase with an increase in the order which will reduce the simulation speed and increase the memory requirement. 4.2.2 Model Validation G4FET models based on Lagrange polynomial are developed from experimental and TCAD Sentaurus training data for both p-channel and n-channel transistors. The order of the polynomial is determined by the number of data points used to develop the model. Then the model is validated using a comparison of current-voltage characteristics between another set of test data and model prediction. 4.2.2.1 An n-Channel G4FET Simulated with TCAD Sentaurus (Device 1) An n-channel G4FET was designed and simulated in TCAD Sentaurus. Table 4.1 gives the device geometry, doping levels and biasing conditions applied in generating the training data. Here, VJG is the voltage applied at both left and right junction-gates. The junction-gates were tied together during the simulations. The training data are used to develop a Lagrange polynomial model of the drain current, ID as a function of four independent variables VDS, VTG, VBG and VJG according to the method described in section 4.2.1. The order of top-gate voltage VTG, bottom-gate voltage VBG and junction-gate voltage VJG are chosen to be 5, 5 and 10, respectively. 35 Table 4.1: Geometry, Doping and Biasing for an n-Channel G4FET Geometry (µm) Doping Concentration (cm-3) Terminal Voltage (V) Length 1.5 Epi silicon 2.0x1017 (Phosphorus) Top-gate (VTG) 0 to 5 V in 0.5 V increment Width 0.4 Poly gate 1020 (Boron) Bottom-gate (VBG) 0 to -15 V in 3 V decrement Gate oxide thickness .01 Both junction- gate 2.0x1020 (Boron) Left junction- gate (VJG) 0 to -5 V in 0.5 V decrement Buried oxide thickness 0.1 Source 1020 (Phosphorus) Right junction- gate (VJG) 0 to -5 V in 0.5 V decrement Active epi silicon layer thickness 0.1 Drain 1020 (Phosphorus) Drain sweep (VDS) 0 to 5 V in 0.05 V increment The drain current versus the drain-source voltage and the corresponding relative errors from TCAD data and Lagrange model are shown in Figures 4.1 and 4.2, respectively for a test biasing condition (VBG = 0 V, VTG = 3.5 V and VJG = 0 V). The effect of model order on predictive accuracy is shown by changing the order of VDS from 5 to 25. The Chebyshev nodes for different orders are shown in the independent axis. The extrapolation of model behavior outside the modeling range is also shown. As evident from this figure, the accuracy improves with the increase in the order resulting in a reduction in mean relative error. In Figure 4.3, the junction-gate voltage, VJG has been varied from 0 to -4 V with the top- gate voltage fixed at 3.5 V and for each of the junction-gate bias TCAD data and model predictions are superimposed. The order of VDS is chosen to be 8 and from the corresponding mean relative error, it is shown that the model fits reasonably well for all the isolines. 36 Figure 4.1: Drain current versus drain-source voltage from TCAD data and Lagrange model for different orders of VDS for an n-channel G4FET. Figure 4.2: Relative errors between TCAD data and Lagrange model for different orders of VDS for an n-channel G4FET. 37 Figure 4.3: Isolines of test data and model for different junction-gate voltages ranging from -4 V to 0 V in 1 V increment with order of VDS fixed at 8. 4.2.2.2 Experimental Data from an n-Channel G4FET (Device 2) Device 2 is an n-channel transistor and has been fabricated in a conventional partially- depleted SOI (PDSOI) technology. The width and length of the device are 0.4 µm and 0.9 µm, respectively. Lagrange polynomial interpolation is used to model the current-voltage characteristics of the device from experimental data. For the model development, the drain source voltage VDS was fixed at 50 mV, the bottom- gate voltage VBG was swept from -5 V to 5 V in 2 V increment, the