To the Graduate Council: I am submitting herewith a dissertation written by M. Nance Ericson entitled “High-Tem- perature, High-Resolution A/D Conversion Using 2nd- and 4th-Order Cascaded Σ∆ Modu- lation in 3.3-V 0.5µm SOS-CMOS.” I have examined the final electronic copy of this dissertation for form and content and recommend that it be accepted in partial fulfillment of the requirements for the degree of Doctor of Philosophy, with a major in Electrical Engineering. James M. Rochelle Major Professor We have read this dissertation and recommend its acceptance: Charles L. Britton, Jr. Benjamin J. Blalock Donald W. Bouldin Vasilios Alexiades Accepted for the Council: Dr. Anne Mayhew Vice Provost and Dean of Graduate Studies (Original signatures are on file with official student records.) High-Temperature, High-Resolution A/D Conversion Using 2nd- and 4th-Order Cascaded Σ∆ Modulation in 3.3-V 0.5µm SOS-CMOS A Dissertation Presented for the Doctor of Philosophy Degree The University of Tennessee, Knoxville M. Nance Ericson August 2002 ii Dedication This dissertation is dedicated to my loving wife, Helen, and to my wonderful son, Stephen, who have provided much encouragement and support throughout this research. iii Acknowledgements I wish to thank Drs. Rochelle, Britton, Bouldin, Blalock, and Alexiades for their guid- ance as my committee. I especially want to thank my major professor, Dr. Rochelle, and colleague Dr. Britton, for their consistent encouragement and mentoring throughout my entire graduate experience. In addition, I want to thank Dr. Bobrek for his technical advice and valuable help throughout this work, and Dr. Clonts for his assistance in ASIC layout and simulation. Many of my colleagues and friends provided support and encouragement that I want to mention: Dr. Gleason, Mike Emery, Dr. Paulus, Dr. Wintenberg, Dr. Smith, and Dr. Simp- son. I also want to thank the management of the project under which much of this work was performed, specifically Dr. Roger Schultz and Tony Moore. I also thank Alex Bobrek, who wrote much of the data collection and signal processing software associated with this research. I thank the staff at Oak Ridge National Laboratory, particularly Bill Bryan, Gary Alley, Dan McDonald, and Janet Swift for their support of my 2-year educational sabbati- cal that was instrumental in my decision to pursue this PhD. I also want to thank Gayle Jones and Kathy Martin for their help in preparing this document, and Norm Cooper of Mustagh Resources, Inc. and Mike Wolfe of Audio Precision, Inc. for helpful discussions. Finally, I want to thank my parents and family for their encouragement and support. iv Abstract Sigma Delta Modulation is an oversampling technique commonly used in high-resolu- tion analog-to-digital conversion. By employing oversampling and quantization noise shaping, the method allows very high-resolution conversion using low-resolution func- tional blocks. A multitude of architectural variations of this oversampled class of digitiz- ers has been explored and reported in research literature for a wide variety of applications including seismic imaging, general low-bandwidth high-resolution instrumentation, audio conversion, and most recently high-speed communications. Data conversion associated with seismic imaging has been recently dominated by this class of converters, though all data acquisition systems require environmental control, pre- venting placement of the digitizing electronics down-hole. The potential improvement in seismic imaging system performance afforded by down-hole placement of electronics is very significant. The use of sensor-localized data collection nodes will provide the optimal sensor interface, both in terms of connectivity and noise, and allow distributed parallel collection and processing of sensor signals. The use of spread spectrum communications methods for up-hole data transmission significantly increases the data integrity and poten- tial throughput. However, in order to realize this improved system partitioning, the high- resolution data converters must be designed to meet operational specifications at elevated temperatures. This research addresses the issue of high-resolution data conversion at elevated tem- peratures, with an emphasis on applicability to down-hole seismic imaging. Sigma delta modulation methods are employed and the theoretical best topology selected for imple- v mentation. Variations in target integrated circuit processes are considered and the most appropriate process for high-temperature implementation employed. A prototype sigma delta ADC was designed, fabricated, and fully characterized over temperature. The results of this research provides the first high-resolution digitizing front-end suitable for down- hole seismic imaging applications and lays the foundation for future high-temperature ADC research. vi Table of Contents 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2. Seismic Imaging Methods & Instrumentation . . . . . . . . . . . . . . . . . . . . . 1 1.3. Overview of High-Temperature Fabrication Processes . . . . . . . . . . . . . . 6 1.4. Dissertation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. Analog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1. Nyquist-Rate Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2. Oversampling Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3. Noise Shaping Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4. Multi-bit Quantizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5. Oversampling, Noise Shaping and Multi-Bit Quantization . . . . . . . . . . 27 3. Sigma Delta ADC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1. Single Loop Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2. Cascaded Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3. Digital Noise Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4. Review of the Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5. Modulator Design & Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.1. Modulator Architectural Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.2. Modulator Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3. Noise Reduction Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.1. Chopping Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.2. Correlated Double Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.4. Modulator Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.5. Modulator Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.6. Integrator Capacitor Value Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.7. Modulator System Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . 64 5.8. Integrator Opamp Design & Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.9. Regenerative Comparator Design & Simulation . . . . . . . . . . . . . . . . . . 82 5.10. Digital-to-Analog Converter (DAC) Design & Simulation . . . . . . . . . 85 5.11. Timing Generator Circuits Design & Simulation . . . . . . . . . . . . . . . . . 86 5.12. Integrator Switches Design & Simulation . . . . . . . . . . . . . . . . . . . . . . 88 5.13. Buffer Amplifier Design & Simulation . . . . . . . . . . . . . . . . . . . . . . . . 90 5.14. Modulator Bias Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.15. Switched-Capacitor 2-2c Cascade Modulator . . . . . . . . . . . . . . . . . . . 96 5.16. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6. Modulator Component Measurement Results . . . . . . . . . . . . . . . . . . . . . . . 101 6.1. Test Method Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.2. Integrator Opamp Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.2.1. Open Loop Gain - Fixed Temperature & Variable Bias . . . . . . . 106 6.2.2. Open Loop Gain - Fixed Bias & Variable Temperature . . . . . . . 109 6.2.3. Noise Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.2.4. Measurement Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 vii 6.2.5. Comparison of Measured and Simulation Data . . . . . . . . . . . . . . 119 6.3. Comparator Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.4. Buffer Amplifier Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.5. Other Block Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7. Σ∆ Modulator ASIC Implementation & Experimental Results . . . . . . . . . . 129 7.1. ASIC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.2. Parameters for Modulator Performance Evaluation . . . . . . . . . . . . . . . 131 7.3. Modulator Test Method & System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.3.1. Test System Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.3.2. Test System Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.4. Modulator Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.4.1. Initial ASIC & Test System Checkout . . . . . . . . . . . . . . . . . . . . . 143 7.4.2. Modulator Output Spectra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.4.3. SNR & SNDR Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 7.4.4. Total Harmonic Distortion (THD) Measurements . . . . . . . . . . . . 164 7.4.5. Dynamic Range Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.4.6. SNR Results vs. Oversampling Ratio . . . . . . . . . . . . . . . . . . . . . 172 7.4.7. Modulator Noise Measurements and Predictions . . . . . . . . . . . . 178 7.4.8. Modulator Performance Prediction . . . . . . . . . . . . . . . . . . . . . . . 183 7.4.9. Tonal Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 7.4.10. Modulator Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . 192 7.4.11. Modulator Experimental Results Summary . . . . . . . . . . . . . . . . 192 8. Conclusion & Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 8.1. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 8.2. Future Research Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 BIBLIOGRAPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 APPENDICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 A. Device Noise Measurements & Analysis . . . . . . . . . . . . . . . . . . . . . . . 215 B. Σ∆ Modulator Test & Analysis System Verification . . . . . . . . . . . . . . . 234 C. Related Paper Submissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 VITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 viii List of Tables Table 4.1: Published single-loop Σ∆ modulators from 1988-2001 . . . . . . . . . 38 Table 4.2: Published cascade Σ∆ modulators from 1988-2001 . . . . . . . . . . . . 39 Table 4.3: Published SOS/SOI Σ∆ modulators from 1988-2001. . . . . . . . . . 43 Table 5.1: Theoretical resolution as a function of M and L (N=1). . . . . . . . . 47 Table 5.2: Modulator sources of error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 5.3: Target integrator opamp design specifications. . . . . . . . . . . . . . . . 67 Table 5.4: Opamp design parameters and associated relationships for folded cascode topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 5.5: Amp2b device information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 5.6: Amp2b_bias device information. . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 5.7: Simulated Amp2b open loop dc gain vs. temperature & bias current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 5.8: Amp2b simulation summary vs. temperature (ibias=50µA, Cload=20pF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 5.9: Simulated integrator opamp noise. . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 5.10: Regenerative comparator device information. . . . . . . . . . . . . . . . . 84 Table 5.11: Integrator buffer amplifier target specifications. . . . . . . . . . . . . . . 92 Table 5.12: Buffer amplifier device information. . . . . . . . . . . . . . . . . . . . . . . . 93 Table 5.13: Buffer amplifier simulation summary vs. temperature. . . . . . . . . . 95 Table 6.1: Amp2b measurement summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 6.2: Measured Amp2b Aol & GBW vs. Ibias (T=25 C, chip 3). . . . . 109 Table 6.3: Amp2b eni measurement summary (T=25 C). . . . . . . . . . . . . . . 117 Table 6.4: Amp2b measurement summary vs. temperature (Ibias=50µA). . 118 Table 6.5: Amp2b comparison of simulation & measurement data - 1 . . . . . 119 Table 6.6: Amp2b comparison of simulation & measurement data - 2 . . . . . 120 Table 6.7: Buffer amplifier measurement summary. . . . . . . . . . . . . . . . . . . . 128 Table 7.1: Matlab signal processing & plotting program summary. . . . . . . . 142 Table 7.2: Measured peak SNR vs. temperature (144Hz). . . . . . . . . . . . . . . 164 Table 7.3: Summary of measured DR vs. temperature. . . . . . . . . . . . . . . . . 171 Table 7.4: Estimated relative output noise densities taken from measured data vs. T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 7.5: Comparison of measured and predicted modulator performance vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 7.6: Calculated peak SNR for 2nd-order modulator (T=25 C). . . . . . 187 Table 7.7: Modulator power supply partitioning. . . . . . . . . . . . . . . . . . . . . . 193 Table 7.8: Modulator measured power consumption vs. temperature. . . . . . 193 Table 7.9: Modulator test parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 7.10: Measured performance summary vs. temperature (chip 4). . . . . . 194 ° ° ° ix List of Figures Figure 1.1. Surface seismic imaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 1.2. Transmission mode seismic imaging methods. . . . . . . . . . . . . . . . 3 Figure 1.3. Instantaneous floating point (IFP) amplifier . . . . . . . . . . . . . . . . . 5 Figure 1.4. Seismic system electronics configurations. . . . . . . . . . . . . . . . . . . 7 Figure 1.5. Comparison of CMOS fabrication technologies. . . . . . . . . . . . . . . 9 Figure 2.1. Quantizer diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2.2. 3-bit quantizer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 2.3. Quantization noise uniform probability density distribution . . . . 15 Figure 2.4. Σ∆ ADC Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 2.5. Basic feedback modulator block diagram . . . . . . . . . . . . . . . . . . 20 Figure 2.6. Feedback modulator architectural development (diagram 1). . . . 23 Figure 2.7. Feedback modulator architectural development (diagram 2). . . . 24 Figure 2.8. 2nd-order interpolative modulator - general case . . . . . . . . . . . . . 24 Figure 2.9. Noise shaping as a function of integrator order. . . . . . . . . . . . . . 25 Figure 2.10. Noise shaping and integrator order (zoom view). . . . . . . . . . . . . 26 Figure 3.1. Σ∆ modulator architectural comparison. . . . . . . . . . . . . . . . . . . . 28 Figure 3.2. 1-1 cascade modulator architecture. . . . . . . . . . . . . . . . . . . . . . . 32 Figure 3.3. 2-2 cascade modulator architecture. . . . . . . . . . . . . . . . . . . . . . . 32 Figure 3.4. Digital noise cancellation for 2-2 cascade architecture. . . . . . . . 35 Figure 3.5. Digital noise cancellation diagram . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 4.1. Resolution vs. speed (published modulators 1988-2001). . . . . . . 41 Figure 4.2. Power efficiency vs. speed (published modulators 1988-2001). . 42 Figure 5.1. Theoretical modulator resolution vs. L and M for N=1 . . . . . . . . 47 Figure 5.2. 2-2 cascade modulator topology selected for implementation . . 50 Figure 5.3. MIDAS simulation results for the 2-2c modulator architecture . 52 Figure 5.4. CDS noise shaping characteristic . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 5.5. Standard switched-capacitor integrator with clocks . . . . . . . . . . 60 Figure 5.6. Switched-capacitor integrator with chopper and clocks . . . . . . . 62 Figure 5.7. Integrator capacitance model. (a) phase 2 and (b) phase 1 . . . . . 67 Figure 5.8. Fully differential folded cascode opamp with CMFB loop . . . . . 68 Figure 5.8. Fully differential folded cascode opamp with CMFB loop . . . . . 68 Figure 5.9. Bias generator circuit for Amp2b . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 5.10. Amp2b dc open loop gain vs. bias current and temperature . . . . 75 Figure 5.11. Amp2b dc open loop gain vs. temperature and bias current . . . . 75 Figure 5.12. Simulated Amp2b open loop gain magnitude (Cload=20pF) . . . 77 Figure 5.13. Simulated Amp2b open loop gain phase (Cload=20pF). . . . . . . . 77 Figure 5.14. Simulated Amp2b output characteristics vs. temperature for T=25 C and T=200 C (Cload=20pF). . . . . . . . . . . . . . . . . . 78 Figure 5.15. Simulated Amp2b slew rate vs. temperature . . . . . . . . . . . . . . . . 78 Figure 5.16. Simulated Amp2b output swing characteristics vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 5.17. Simulated Amp2b input-referred noise vs. temperature ° ° x (using foundry supplied models) . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 5.18. Regenerative comparator schematic and timing diagram. . . . . . . 83 Figure 5.19. Simulated comparator performance at T=25 C (1mV input) . . . 84 Figure 5.20. Simulated comparator performance at T=200 C (1mV input) . . 85 Figure 5.21. DAC circuit diagram with break-before-make switch control. . . 86 Figure 5.22. 2-phase non-overlapping clock generator - standard clocks. . . . . 87 Figure 5.23. 2-phase non-overlapping clock generator - chopper clocks . . . . 88 Figure 5.24. Clock generators simulation results at T=25 C . . . . . . . . . . . . . 89 Figure 5.25. Clock generators simulation results at T=200 C . . . . . . . . . . . . 89 Figure 5.26. Transmission gate switch with dummy devices (tg5, tg10) . . . . . 90 Figure 5.27. Simulated on-resistance vs. temperature for (a) tg5 and (b) tg10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 5.28. Buffer amplifier used for observing integrator outputs . . . . . . . . 93 Figure 5.29. Simulated buffer amplifier open loop gain vs. temperature . . . . 94 Figure 5.30. Simulated buffer amplifier open loop phase vs. temperature . . . 94 Figure 5.31. Buffer amplifier output characteristics vs. temperature . . . . . . . . 95 Figure 5.32. Bias cells. (a) integrator opamp, and (b) integrator buffer opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 5.33. Switched capacitor 2-2c cascaded modulator block diagram . . . 97 Figure 5.34. Simulation results of modulator layout extraction showing integrator outputs and integrator clocks (T=25 C) . . . . . . . . . . . 98 Figure 5.35. Simulation results of modulator layout extraction showing integrator outputs and integrator clocks (T=200 C) . . . . . . . . . . 99 Figure 6.1. Micro-photograph of sdmod4_parts2 test chip. . . . . . . . . . . . . . 101 Figure 6.2. Modulator components test PCB schematic - part A. . . . . . . . . 103 Figure 6.3. Modulator components test PCB schematic - part B. . . . . . . . . 103 Figure 6.4. Photograph of modulator components test PCB. . . . . . . . . . . . . 104 Figure 6.5. Amp2b open loop measurement block diagram. . . . . . . . . . . . . 106 Figure 6.6. Measured Amp2b open loop response vs. bias current (T=25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 6.7. Measured Amp2b open loop response vs. bias current . . . . . . . 107 Figure 6.8. Measured Amp2b dc open loop gain vs. bias current (T=25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 6.9. Measured Amp2b 0dB crossover vs. bias current (T=25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 6.10. Measured Amp2b open loop characteristics vs. temperature. . . 110 Figure 6.11. Measured Amp2b open loop dc gain vs. temperature (zoom view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 6.12. Measured Amp2b open loop dc gain in dB vs. temperature. . . . 111 Figure 6.13. Measured Amp2b 0dB crossover vs. temperature . . . . . . . . . . . 112 Figure 6.14. Measured Amp2b output swing. . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 6.15. Measured Amp2b differential slew rate vs. temperature (neg. transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 6.16. Measured Amp2b differential slew rate vs. temperature (pos. transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 ° ° ° ° ° ° ° ° ° xi Figure 6.17. Amp2b noise measurement setup. . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 6.18. Amplifier used for noise measurement. . . . . . . . . . . . . . . . . . . . 115 Figure 6.19. Measured Amp2b input-referred noise vs. bias current, T=25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 6.20. Measured and simulated Amp2b input-referred noise . . . . . . . . 116 Figure 6.21. Comparison of measured and simulated Amp2b Aol vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 6.22. Comparison of measured and simulated Amp2b GBW vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 6.23. Measured and simulated Amp2b loop gain vs. temperature. . . . 122 Figure 6.24. Measured comparator output waveforms at T=25 C. . . . . . . . . 125 Figure 6.25. Measured comparator output waveforms at T=25 C (zoom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 6.26. Measured buffer amplifier output as 1X buffer (T=25 C). . . . 126 Figure 6.27. Measured buffer amplifier output as 1X buffer - pos. edge (T=25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 6.28. Measured buffer amplifier output as 1X buffer - neg. edge (T=25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 7.1. Microphotograph of the 2-2c cascade modulator ASIC fabricated in 0.5µm SOS-CMOS process. . . . . . . . . . . . . . . . . . 131 Figure 7.2. Modulator test & characterization system. . . . . . . . . . . . . . . . . 134 Figure 7.3. Modulator test PCB schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 136 Figure 7.4. Modulator bias circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Figure 7.5. Modulator test system boards. . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 7.6. Photograph of modulator test & characterization system. . . . . . 137 Figure 7.7. LabView based data acquisition software block diagram . (a) diagnostics mode (b) data collection mode. . . . . . . . . . . . . . 138 Figure 7.8. LabView data acquisition program setup menus . . . . . . . . . . . . 140 Figure 7.9. Diagnostics mode output plot. . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 7.10. Nuttall window characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 7.11. Measured modulator clocks for T=25 C. . . . . . . . . . . . . . . . . . 145 Figure 7.12. Measured modulator clocks for T=200 C. . . . . . . . . . . . . . . . . 146 Figure 7.13. Measured modulator output spectra . . . . . . . . . . . . . . . . . . . . . . 147 Figure 7.14. 2nd-order modulator measured output spectra. . . . . . . . . . . . . . 149 Figure 7.15. 2nd-order modulator measured output spectra. . . . . . . . . . . . . . 150 Figure 7.16. 2nd-order modulator measured output spectra. . . . . . . . . . . . . . 151 Figure 7.17. 4th-order modulator measured output spectra. . . . . . . . . . . . . . . 152 Figure 7.18. 4th-order modulator measured output spectra. . . . . . . . . . . . . . . 153 Figure 7.19. 4th-order modulator measured output spectra. . . . . . . . . . . . . . . 154 Figure 7.20. Measured SNR vs. input level and temperature - chip 2 . . . . . . 156 Figure 7.21. Measured SNR vs. input level and temperature - chip 3 . . . . . . 157 Figure 7.22. Measured SNR vs. input level and temperature - chip 4 . . . . . . 158 Figure 7.23. Measured SNDR vs. input level and temperature - chip 2 . . . . 159 Figure 7.24. Measured SNDR vs. input level and temperature - chip 3 . . . . 160 Figure 7.25. Measured SNDR vs. input level and temperature - chip 4 . . . . 161 ° ° ° ° ° ° ° ° xii Figure 7.26. Measured peak SNR vs. temperature . . . . . . . . . . . . . . . . . . . . . 162 Figure 7.27. Measured peak SNR vs. temperature (all chips, 144Hz). . . . . . 163 Figure 7.28. Measured THD vs. input level and temperature - chip 2 . . . . . . 165 Figure 7.29. Measured THD vs. input level and temperature - chip 3 . . . . . . 166 Figure 7.30. Measured THD vs. input level and temperature - chip 4 . . . . . . 167 Figure 7.31. Dynamic range (DR) graphical calculation method. . . . . . . . . . 168 Figure 7.32. Measured DR vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Figure 7.33. Measured DR vs. temperature for 2nd- and 4th-order modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 7.34. Measured SNR vs. input level & temperature . . . . . . . . . . . . . . 172 Figure 7.35. 2nd-and 4th-order modulator output spectra. . . . . . . . . . . . . . . . 173 Figure 7.36. Effect of oversampling ratio (M) on modulator SNR performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 7.37. Measured peak SNR vs. OSR & temp. for chips 2 & 3 . . . . . . . 175 Figure 7.38. Measured peak SNR vs. OSR & temp. for chip 4 . . . . . . . . . . . 176 Figure 7.39. Modulator output spectrum showing flicker and white noise components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Figure 7.40. Modulator output spectrum with chopper enabled . . . . . . . . . . 180 Figure 7.41. Comparison of chopped and unchopped modulator output vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Figure 7.42. Output noise spectral densities from measured data vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Figure 7.43. Measured and simulated eni using foundry supplied and fitted noise models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Figure 7.44. Demodulation of tonals into baseband (chopper disabled). . . . . 189 Figure 7.45. Demodulation of tonals into baseband (chopper enabled). . . . . 191 1 CHAPTER 1 INTRODUCTION 1.1 Background The goal of this research is to develop a high-resolution data converter suitable for the high temperature environment associated with down-hole seismic imaging. This section reviews general seismic imaging methods and associated measurement requirements, and provides an overview of the progression of commercially available instrumentation designed to address the specific needs of this field. 1.2 Seismic Imaging Methods & Instrumentation Seismic methods employ sound waves to characterize subsurface formations in the earth’s crust. Variations in geology filter the traveling acoustic waves. The variation in the traveling waves arriving at a sensor array are detected, processed, and used to deter- mine the location and volume of oil and gas deposits. These variations are the result of reflection and refraction of the traveling wave and are observed as phase and amplitude effects. Using a number of processing algorithms, the multi-sensor data is then used to produce an image of the interrogated region. This general method is widely applied to both oil and gas exploration and oil well management, as well as other geological surveys. In general, seismic methods can be divided into two primary categories: reflection mode and transmission mode. In reflection mode, the acoustic source and the detectors both lie in the same plane, typically placed along the surface of the ground. The sound waves from the source propagate through the medium and some portion are reflected by 2 subsurface features back to the detector array. Transmission mode requires that the source and detector arrays be located on opposing sides of the imaged medium. Of the two meth- ods, reflection mode is the least invasive as both the source and detector array are typically located on the surface. However, in passing through the weathered layer twice, the acous- tic waves are both low-pass filtered and significantly attenuated, resulting in received sig- nals that are band-limited to the 8-120 Hz range. Reflection mode most commonly refers to Surface Seismic techniques (see Fig. 1.1). Transmission mode includes both Vertical Surface Propagation (VSP) and Cross-Well (CW) techniques (see Fig. 1.2). In VSP, the source is located on the surface and an array of detectors is placed in a vertical well. This approach has the advantage of only one pass through the surface or weathered layer. CW is an extension of VSP that eliminates propagation through the weather layer altogether by employing two wells, one having the source array and the other the detector array. This approach eliminates the effects of the weathered layer resulting in higher bandwidth sig- nals (typically 8-2000 Hz). Detector arrays with readout electronics of sufficient sampling bandwidth and dynamic range can be employed for use in either transmission- or reflec- tion-mode seismology. Other variations to these commonly used methods exist including hybrid approaches that fuse data from multiple methods. The most demanding operational specification for digital seismic recorders is dynamic range. Due to the absorption properties of the earth, a large amount of acoustical energy has to be applied by the excitation source. Each acoustic sensor will detect both the initial direct acoustic wave along with many attenuated reflected/refracted components resulting in very demanding dynamic range requirements. 3 Surface Excitation Data Acquisition Oil/Gas Deposit Weathered Layer Surface Sensor Figure 1.1 Surface seismic imaging. Surface Acoustic Source Application Sensor Array Data Acquisition Oil/Gas Deposit Weathered Layer Acoustic Source Borehole Sensor Array Data Acquisition Oil/Gas Deposit Weathered Layer Figure 1.2 Transmission mode seismic imaging methods. (a) Vertical Seis- mic Profiling (VSP) and (b) Cross Well (CW). (a) (b) 4 This dynamic range is further complicated by having sensors at the surface near the sources, and sensors at distances exceeding 10,000 ft. downhole. For these reasons, sen- sors and readout electronics with large dynamic range (16-24 bits) are required for high resolution imaging. Early seismic recorders stored analog signals from sensor arrays directly to magnetic tape. In the 1980s, digital seismic recorders emerged that digitized and stored the data using limited resolution analog-to-digital converters (ADCs). To increase the overall dynamic range beyond that offered by then state-of-the-art ADCs, the integer floating point (IFP) amplifier was developed [33,77,132,170,177,178,179]. IFP techniques are based on using a variable gain amplifier with binary weighted gains. At the beginning of each sampling cycle, the optimum gain for each sensor channel is determined and applied prior to digitization. The optimum gain is that which causes an ADC output code between one-half and full scale, or where the ADC most significant bit (MSB) equals 1. The out- put of the IFP block is then input to a moderate resolution ADC (12-16 bits). Using binary weights allows the gain code bits to be added to the ADC output code as the MSBs. Fig. 1.3 shows a block diagram for a typical IFP amplifier system. A track and hold is used to allow time for the optimum channel gain to be determined. Often two IFP channels are used for a single signal channel to allow sufficient time for gain selection and amplifier settling. The IFP channel of Fig. 1.3 has a 20-bit intrinsic dynamic range (120.4 dB). Though IFP topologies do provide an improvement in dynamic range over fixed gain topologies, the use of switched, high-gain front-ends produce a number of complications that make practical implementation and use difficult. High performance track and hold and gain circuits are essential requiring calibration of each gain stage and separate offset 5 correction of both the track and hold circuits and each of the gain stages. The use of mul- tiple variable-gain amplifiers introduce errors between different gain ranges, reducing lin- earity and making monotonic operation difficult - particularly over wide temperature ranges. In addition, complex control for dynamic optimal gain selection is required. Though these problems have been somewhat addressed by topological improvements, dc offset correction methods, and gain correction and calibration procedures [33,77,132,170,177,178,179], the use of IFP in digital seismic recorders came to a com- plete halt in the 1990s with the maturing of a new class of high-resolution, oversampling ADCs employing sigma delta modulation. However, no commercial or research literature has addressed placing the high-resolution data converters down-hole, due to extreme tem- perature ranges required and associated complications. Though many commercially available ADCs indicate 24-bit resolution, the effective resolution of commercially available ADCs is as high as 22.5 bits @ 5 Hz bandwidth (or 20-bit Digital Result Track & Hold 2x Gain Select Sensor Signal 2x 2x 2x Switch Network 2x Gain Select 2x 2x 2x Switch Network Track & Hold 16-Bit ADC MUX Figure 1.3 Instantaneous floating point (IFP) amplifier. 6 20 bits @ 1 kHz bandwidth) [220]. The specification of 24-bit dynamic range is widely accepted in seismic systems, though a much reduced effective resolution is actually obtained. High-resolution commercially available ADCs are specified for a maximum temperature range of -40 C to 85 C with most units specified over a more limited range of 0 C to 70 C. Clearly, the temperature variations anticipated in the target application (0 C to 160 C) far exceed the specifications of any available over-sampled data con- verter. The target application for this research is conventional VSP seismic systems that cur- rently employ surface electronics and down-hole sensors at depths up to 10000 ft. Signif- icant signal degradation associated with long distance sensor cable could be eliminated if a sensor-localized ADC were available. This would enable packetized digital data transfer and improve the fidelity of sensitive sensor signals. In addition, a system topology based on smart, sensor-localized nodes provides a number of advantages including digital data transfer, localized signal processing, increased signal channel number, and advanced mon- itoring and reporting functions. A block diagram of this improved system architecture is shown in Fig. 1.4 along with the conventional topology consisting of surface electronics, for comparison. However, the temperature limitations of existing commercial ADCs pro- hibit the design of such a system. 1.3 Overview of High-Temperature Fabrication Processes In recent years, Silicon-On-Insulator (SOI) CMOS technology has emerged as the dominant technology for the realization of high-temperature integrated circuits. A number of research publications have demonstrated operation of SOI CMOS circuits at tempera- ° ° ° ° ° ° 7 tures up to 300 C [38,39,48,61,65]. SOI integrated circuit fabrication technology offers many performance advantages over the industry standard bulk CMOS process technolo- gies. Significant reduction in leakage current and substrate induced noise, and improve- ment in maximum operational speed and power efficiency are the most significant performance improvements of SOI over bulk CMOS. Other advantages of SOI over bulk CMOS include latch-up immunity and lower parasitic capacitances. Disadvantages of SOI as compared to bulk CMOS include higher material cost, reduced availability, higher defect density, and higher thermal resistivity resulting in increased self-heating [59,123]. SOI is a general category that is composed of two primary technologies - Separation by IMplantation of OXygen (SIMOX) and Silicon-On-Sapphire (SOS). SIMOX starts with a silicon substrate that is implanted with oxygen to form an insulator layer (buried RF Receivers Surface Data Collection System Σ∆ ADC Digital Controller/Signal Processing/Spread Spectrum Modulation Power Conditioning Sensor Suite RF Transmitter Down-Hole Data Collection & Processing Node R ug ge di ze d C oa x C ab le Signal Conditioning Power Single Ruggedized Coax Cable Surface ~ 10 ,0 00 f t. Figure 1.4 Seismic system electronics configurations. (a) Conventional sur- face-based system, and (b) proposed distributed system. (a) (b) Surface n cables for n sensors ~ 10 ,0 00 f t. Surface Data Acquisition System ° 8 oxide layer) just under the surface. Devices are then constructed using the surface layer (as in bulk) resulting in a CMOS technology that is electrically isolated from the substrate. SOS was first developed and used in the 1970s for applications in high radiation envi- ronments. The SOS process begins with a sapphire insulating substrate. A thin epitaxial layer of silicon is grown, and doped to form the drain, source, and channel regions of tran- sistors. These doped areas extend to the sapphire insulator effectively eliminating signifi- cant back-gate biasing. Early application of the technology was very limited due to the high cost of fabrication and the defects associated with the silicon/oxide interface. How- ever, recent advances in processing have made SOS a competitive technology with SIMOX and bulk CMOS. The advantages of SOS as compared to bulk is the same as those mentioned for SIMOX, namely reduced leakage currents, higher speed due to reduced parasitic capaci- tance, reduced substrate induced noise, and latch-up immunity. One difference is that SIMOX does have backgate biasing not present in SOS. Silicon-On-Sapphire was chosen as the fabrication technology for this research due to the availability of an SOS fabrication process through MOSIS, and the lack of backgate bias in SOS devices. Fig. 1.5 shows the primary physical differences between SIMOX, SOS, and bulk CMOS processing. 1.4 Dissertation Overview This research addresses the specific problem of high-temperature, high-resolution data conversion associated with the placement of data acquisition electronics down-hole. This goal will be realized by employing sigma delta modulation techniques, appropriate modu- 9 P-Substrate (Silicon) P+ P+ P+N+ N+N+ N-Well Metal 1 SiO2 P-Substrate (Silicon) P+ P+ P+N+ N+N+ N-Well Metal 1 Silicon Substrate Buried oxide SiO2 P-Substrate (Silicon) P+ P+ P+N+ N+N+ N-Well Metal 1 Sapphire Substrate oxide SiO2 (a) (b) (c) Figure 1.5 Comparison of CMOS fabrication technologies. (a) Bulk CMOS, (b) separation by implantation of oxygen SIMOX, and (c) Silicon- on-sapphire (SOS). 10 lator topology selection, proper fabrication process selection, and circuit design methods to maximize high-temperature performance and survivability. This dissertation is organized into 8 chapters. Chapter 1 provides a general overview of the field of seismic imaging and summarizes the types of instrumentation historically applied to this field. The performance and environmental requirements for down-hole seismic instrumentation is reviewed emphasizing the associated difficulty of addressing the data acquisition needs of this field. In Chapter 2, the concept of analog-to-digital con- version is introduced with an emphasis on theoretical performance comparisons of Nyquist rate and oversampled data converter types (Σ∆). Chapter 3 provides an overview of candidate Σ∆ modulator architectures and compares the relative advantages and disad- vantages of each topology. Having introduced the concept of Σ∆ modulation and associ- ated terms, Chapter 4 provides a detailed review of the modulators published in open literature. Comparisons between single loop and cascaded architectures are made using two published performance metrics and a new performance metric introduced specifically for this research. A summary of the limited published results of modulators either fabri- cated in SOI/SOS CMOS or tested at elevated temperatures is presented and the specific need for this research is established. In Chapter 5, justifications for the modulator topol- ogy and associated parameters are given and the modulator design is outlined, including the design of both the circuit modules and the overall modulator. Simulation results are given where appropriate. Chapter 6 presents results of modulator circuit blocks tested from 25 C-200 C fabricated in SOS-CMOS. Comparisons to the simulations of Chapter 5 are provided when appropriate. Test results from the first 4th-order modulator fabricated in SOS are presented in Chapter 7 and compared to a 2nd-order modulator fabricated on ° ° 11 the same chip. All modulator tests are performed over a temperature range of 25 C- 200 C. Details on the chip design, test methodology, test system hardware, and associ- ated signal processing are also provided. Finally, Chapter 8 provides a conclusion of the research and identifies future directions for the furthering of this work. ° ° 12 CHAPTER 2 ANALOG-TO-DIGITAL CONVERTERS An analog-to-digital converter (ADC) converts an analog signal composed of a contin- uum of values to a digital result. The ADC output is a digital best approximation of its input signal, with the approximation error (or quantization error) being related to the ADC resolution. ADCs can be classified as one of two types: Nyquist-rate or oversampling. Nyquist rate converters sample the input signal at approximately twice the highest fre- quency of the input signal using a number of different architectures including successive approximation, pipeline, algorithmic, and flash. Oversampling converters achieve improved resolution at the expense of conversion speed. Improved performance is accom- plished by sampling the input signal at rates much higher than the Nyquist rate and shap- ing the quantization noise using single-loop low order, single-loop high order, cascaded, multi-rate, and multi-bit feedback loops, and associated combinations. In this section, analytical expressions are developed demonstrating the advantages offered by Σ∆ modulation techniques over Nyquist rate converters. 2.1 Nyquist-Rate Converters In an ADC, the relationship between the input voltage (Vin), the reference voltage (Vref) and the digitized result (b0 - bn) can be represented by (2.1)Vref b12 1– b22 2– … bn2 n– + + +( ) Vin eq+= 13 where eq represents the quantization error associated with the conversion. Thus a quan- tizer maps a continuum of input analog values to a discrete set of output levels. An n-bit quantizer maps an analog input range of values to 2n discrete output levels. A quantizer can be modeled as a linear combination of the input signal x[n] multiplied by the quantizer gain (G), and a noise source e[n] representing the quantization noise: . (2.2) This relationship for a midrise quantizer is illustrated in Fig. 2.1. A midrise quantizer has transition points at the midpoint of its input range. Following the representation given by Rabii [158], the output level steps are defined as (2.3) where ∆ is the maximum output range. Likewise, the input level steps are defined as (2.4) y n[ ] G x n[ ] eq n[ ]+⋅= + e(n) x(n) y(n)x(n) y(n) Figure 2.1 Quantizer diagrams. (a) graphical representation and (b) model including gain and quantization noise component. δ ∆ 2 n 1– --------------= γ Γ 2 n -----= 14 where Γ is the full-scale input range. Using the notation of Eqn. 2.3 and Eqn. 2.4 the quantization characteristics for a ramp input produce a sawtooth quantization error as shown in Fig. 2.2. The linearized gain (G) of the quantizer can be expressed as . (2.5) Clearly, the quantization error is nonlinear. However, a uniform white probability den- sity assumption is valid if the following conditions are met: (a) the input signal does not exceed the input range of the quantizer, (b) the quantizer has a large number of quantiza- tion levels, (c) the input signal is active across many quantizer levels, and (d) the joint probability density of any two quantizer inputs is smooth [10,158,207,209]. Using the white noise approximation, the quantization noise probability density is shown in Fig. 2.3. G δ γ -- ∆ 2 n( ) Γ 2 n 1–( ) -----------------------= = Figure 2.2 3-bit quantizer characteristics. (a) transfer function, and (b) quanti- zation error. output xmin xmax input (x) δ/2 −δ/2 eq δ γ input (x) γ ∆ Γ Γ G=slope (a) (b) 15 The variance of this noise term is equal to the quantization noise power in this case and is expressed at the output as . (2.6) In practice, one or more of the conditions listed above to justify the use of the white noise approximation are not valid. A more rigorous handling of this quantization proba- bility density can be found in a number of contemporary publications [11,26,159]. Though inexact, use of the white noise approximation allows many useful performance metrics to be estimated and will be accepted for this work. The primary performance metric commonly applied to ADCs and of special impor- tance to the seismic industry is dynamic range (DR). Dynamic range is defined as the ratio of the full-scale input power to the power of the input signal when the signal-to-noise ratio is one. The signal-to-noise ratio (SNR) is measured at the output of the converter and equals the ratio of the signal power (Ss) to the quantization noise power (Sq). Figure 2.3 Quantization noise uniform probability density distribution. δ/2-δ/2 ρE(eq) eq 1/δ σq 2 Sq eq 2ρE eq( ) eqd ∞– ∞ ∫ δ2 12 ------= = = 16 Using the unity gain approximation for G, further described in later sections, the SNR of a Nyquist rate converter can be expressed as a power ratio with a sinusoidal input of amplitude A as . (2.7) Alternatively, the SNR can be expressed in dB using the root mean square (rms) values of the input signal and quantization noise: . (2.8) From Eqn. 2.7, the SNR will be unity when the input signal power is δ2/12G2. Conse- quently, the dynamic range can be expressed as . (2.9) Expressed in dB, the dynamic range of a Nyquist rate converter with a n-bit quantizer becomes . (2.10) Thus for a Nyquist rate converter to achieve a DR of 98dB (or 16 bits) requires a 16-bit quantizer. This requirement is beyond the practical achievable accuracy for untrimmed monolithic circuits [105,124] since matching of 1 part in 65536 (0.0015%) element SNR Ss Sq ----- A 2 2 ------ δ2 12 ------ ------ 6A 2 δ2 ---------= = = SNRdB 20 Vinrms Verms ------------log⋅ 20 A 2 ------- δ 12 ---------- ----------log⋅ 20 2A δ ------- 3 2 ---⋅ dB[ ]log⋅= = = DR Γ 2⁄( )2 2 ----------------- δ2 12G 2 ------------- ------------------ γ2 2 2n( ) 8 ------------------ γ2 12 ------ ------------------ 3 2 --- 2 2n( )= = = DRdB 1.76 6.02n+= 17 matching is required. As will be demonstrated, the methods employed in Σ∆ modulation allow much higher dynamic range to be obtained using low-resolution quantizers without high precision element matching. 2.2 Oversampling Converters The previous section outlined the basic relationships between quantizer resolution, quantization noise, DR, and SNR for Nyquist-rate converters. Decreasing the quantile by increasing the quantizer resolution was shown to increase the dynamic range. However, implementation imperfections including matching errors and offsets limit the obtainable resolution of Nyquist rate converters. Oversampling techniques were first introduced by Inose in 1962 and rely on oversam- pling of the input data and application of noise shaping and digital filtering functions to obtain high-resolution conversion [95]. The general topology of a Σ∆ ADC is shown in Fig. 2.4. The circuit is composed of a feedback modulator that shapes the quantization noise to reduce the noise power contribution in the signal bandwidth. Oversampling the input signal further reduces the in-band noise power. After modulation, a digital filter is used to downsample and filter the modulated signal to the Nyquist bandwidth. A sum- mary of the signal spectral content that shows the oversampling, noise shaping, and digital filtering operations is also provided in Fig. 2.4. Oversampling and noise shaping are dis- cussed in more detail in the remaining portions of this section. Using the white noise approximation, oversampling alone has the effect of spreading the quantization noise power over the sampling bandwidth. Thus, a significant reduction 18 Figure 2.4 Σ∆ ADC Overview. (a) block diagram and (b) spectral content. + H(z) - x(t) y[n] quantizer Digital Filter/ Decimator Anti-aliasing Filter Feedback Modulator Y[n]xb(t) fb | x(t) | f | y[n] | f fb fb | xb(t) | f fsfs/2 | Y[n] | f fb fnyquist (a) (b) 19 in the in-band quantization noise can be achieved by simply oversampling. The oversam- pling ratio, M, is defined as , (2.11) where fs is the sampling frequency, fb is the signal-bandwidth, and fn is the Nyquist fre- quency. Oversampling the input by M and downsampling and filtering the modulator out- put to the signal bandwidth reduces the in-band quantization noise power by M. Incorporating oversampling, the dynamic range becomes . (2.12) (2.13) Though oversampling produces a significant increase in the SNR, only a modest improvement is realized that quickly reaches a limit due to the practical aspects of imple- mentation. Oversampling improves the DR by only 3 dB for each doubling of M. Eqn. 2.13 shows that a 1-bit improvement in DR requires a 4X increase in M. A 4-bit improve- ment in DR requires a 256X increase in M. This exponential relationship quickly reaches a practical implementation limit due to the required sampling frequency. In addition, as the dynamic range is increased by increasing M, the linearity requirements of the quan- tizer must be equivalent to the overall dynamic range of the converter [158]. These com- plications make the improvement in dynamic range due to oversampling alone very limited and usually constrains M to 512 or less in most practical implementations. M fs 2fb ------- fs fn ----= = DR Ss Sc M⁄ -------------- 3 2 ---M 2 2n( )= = DRdB 10 Mlog 6.02n 1.76+ += 20 2.3 Noise Shaping Modulators Further improvement in the realizable dynamic range of a converter can be obtained using a feedback architecture to shape the quantization noise so that the majority of the quantization noise is moved outside the signal bandwidth. In this section, the transfer functions for a noise-shaping modulator are developed, and the effect of noise shaping on DR is demonstrated. The basic transfer functions for the input signal and quantization noise of a feedback modulator are easily developed using the block diagram of a feedback system (see Fig. 2.5). Here the ADC (quantizer) is modeled as the gain, G, and additive quantization noise, EQ(z). The DAC is assumed to have the same resolution as the quantizer ADC, resulting in the addition of only implementation error, modeled as ED(z). A(z) and F(z) are dis- crete-time filters. For this analysis, EQ(z) and ED(z) are considered uncorrelated white noise sources. The feedback modulator is a linear, time-invariant system allowing super- position for analysis of the input signal transfer function HX(z), quantization noise transfer function HQ(z) and the DAC noise transfer function HD(z). These transfer functions are developed below. + A(z) F(z) - + X(z) Y(z)+ + G EQ(z) ED(z) Figure 2.5 Basic feedback modulator block diagram. 21 I1(z) represents an intermediate node at the output of the A(z) filter block and can be defined as . (2.14) The output of the modulator becomes . (2.15) Substituting [2.14] into [2.15] yields (2.16) and (2.17) The individual transfer functions for the input signal, X(z), the quantization noise, EQ(z), and the DAC error, ED(z), respectively become: (2.18) (2.19) . (2.20) For a 2nd-order modulator, the desired response is . (2.21) The desired response of the modulator is to pass the input signal and shape the quantiza- tion noise with a high-pass characteristic. I1 A z( ) X z( ) F z( ) Y z( ) ED z( )+( )–[ ]= Y z( ) I1G Eq z( )+( )= Y z( ) GA z( ) X z( ) F z( ) Y z( ) ED z( )+( )–[ ]= Y z( ) X z( ) GA z( ) 1 GA z( )F z( )+ ------------------------------------ EQ z( ) GA z( )F z( ) 1 GA z( )F z( )+ ------------------------------------ ED z( ) 1 1 GA z( )F z( )+ ------------------------------------–    . + + = HX z( ) Y z( ) X z( ) ----------- GA z( ) 1 GA z( )F z( )+ ------------------------------------= = HQ z( ) Y z( ) EQ z( ) -------------- GA z( )F z( ) 1 GA z( )F z( )+ ------------------------------------= = HD z( ) Y z( ) ED z( ) -------------- 1 1 GA z( )F z( )+ ------------------------------------= = Y z( ) z 2– X z( ) 1 z 1– –( ) 2 EQ z( ) z 2– ED z( )–+= 22 For simplification, the error associated with the DAC will be assumed zero, resulting in a modulator output in terms of the input, X(z), and the quantization noise, EQ(z): . (2.22) This requires the following solutions for HX(z) and HQ(z): (2.23) and . (2.24) For the general Lth-order modulator (2.25) and . (2.26) To meet the required forms given by [2.25] and [2.26] (2.27) and . (2.28) This assumes the gain G is unity, (unity-gain approximation). Thus the expression for A(z) is simply an Lth-order integrator with an L-sample delay term. F(z) must be manipu- lated further to obtain an easily realizable form. For example, when L=2, F(z) becomes . Further manipulation produces (2.29) Y z( ) z 2– X z( ) 1 z 1– –( ) 2 EQ z( )+= HX z( ) z 2– = HQ z( ) 1 z 1– –( ) 2 = HX z( ) z L– = HQ z( ) 1 z 1– –( ) L = A z( ) z L– 1 z 1– –( ) L -----------------------= F z( ) z L 1 1 z 1– –( ) L –[ ]= 2z 1– F z( ) 2z 1 z 1– –( ) 1+= 23 which is composed of two feedback terms as shown in Fig. 2.6. Splitting A(z) into two, single order, delayed integrators allows feedback of the non- unity term between the integrators and simplifies the overall feedback function to a pair of feedback gains (see Fig. 2.7). A generalized topology incorporating fixed gains at the inputs of the summing nodes is shown in Fig. 2.8 for the 2nd-order interpolative modulator. The associated z-domain output is given by . (2.30) To obtain the desired modulator output given by [2.22] the following conditions must be met: . (2.31) X(z) Y(z) EQ(z) + z-2/(1-z-1)2 2z(1-z-1) - + + - Figure 2.6 Feedback modulator architectural development (diagram 1). Y z( ) g1 g1 ′ -----       z 2– X z( ) 1 z 1– –( ) 2 EQ1 z( )+ 1 z 1– g2 ′ g1 ′ g2 ----------- 2–       z 2– 2 g2 ′ g1 ′ g2 -----------–       + + -----------------------------------------------------------------------------------= g2 ′ g1 ′ g2 ----------- 2 g1 g1 ′ -----, 1= = 24 X(z) Y(z) EQ(z) + z-1/(1-z-1) - + + - z-1/(1-z-1)+ 2 Figure 2.7 Feedback modulator architectural development (diagram 2). + I1(z) - + X(z) ++ - g1’ g2’ g1 g2 I2(z) Y(z)+G EQ(z) Figure 2.8 2nd-order interpolative modulator - general case. 25 Using the same development strategy, any order of modulator can be obtained by adding additional integrator stages and feedback paths to the interpolative architecture, resulting in the following z-domain output characteristic for an Lth-order modulator: . (2.32) However, interpolative modulator architectures of order >= 3, are at best conditionally sta- ble and must be implemented with caution. The following sections will address architec- tural selection and provide topology alternatives that allow high-order, stable, noise- shaping modulators. The effect of noise shaping on the quantization noise is demonstrated in Fig. 2.9 and Fig. 2.10. In both graphs f actually represents the normalized frequency (f/fs). Y z( ) z L– X z( ) 1 z 1– –( ) L EQ z( )+= 16 0 Order1 f( ) Order2 f( ) Order3 f( ) Order4 f( ) Noshaping f( ) .50 f 0 0.1 0.2 0.3 0.4 0 5 10 15 Figure 2.9 Noise shaping as a function of integrator order. 26 2.4 Multi-bit Quantizers In addition to oversampling and noise shaping, increasing the internal quantizer reso- lution (n) can be used to further increase the achievable dynamic range of a Σ∆ modulator. If properly implemented, the incremental improvement in the obtainable resolution roughly tracks the increase in internal resolution. However, precise implementation of the multi-level error feedback DACs are essential to improve the performance and can signif- icantly reduce the modulator performance if the design is not extremely linear [127]. This is the result of the DAC output being summed at the input of the loop. 1 1.559 10 9. Order1 f( ) Order2 f( ) Order3 f( ) Order4 f( ) Noshaping f( ) .5 32 .001 f 0.005 0.01 0.015 1 10 9 1 10 8 1 10 7 1 10 6 1 10 5 1 10 4 1 10 3 0.01 0.1 1 Figure 2.10 Noise shaping and integrator order (zoom view). 27 2.5 Oversampling, Noise Shaping and Multi-Bit Quantization Combining the effects of oversampling, noise shaping, and multi-bit quantization, Σ∆ modulators have been shown to provide significant increases in achievable dynamic range over Nyquist rate converters. The following expression provides the theoretically obtain- able dynamic range for a Σ∆ modulator as a function of the oversampling ratio (M), noise shaping order (L), and internal quantizer resolution (n) [127] . (2.33) Eqn. 2.33 can also be expressed in bits of resolution (B) as . (2.34) Note that these expressions can be used to calculate the theoretically obtainable resolution and do not account for practical implementation losses or the contribution of electronic noise sources which limit the achievable performance in modulator implementations. In Chapter 3 an overview of candidate modulator topologies is discussed and the associated advantages and disadvantages of the different architectures are summarized. DR Ss Sq ----- 3 2 --- 2L 1+ π2L ----------------    M 2L 1+( ) 2 n 1–( ) 2 = = B bit( ) 1 2 ---log2 2 n 1–( ) 2 2L 1+( ) M 2L 1+( ) π2L -----------------------------------------------------------------       = 28 CHAPTER 3 SIGMA DELTA ADC ARCHITECTURES Many different architectures have been developed for Σ∆ modulator implementation, each providing distinct advantages and disadvantages. Fig. 3.1 provides an overview of the most common modulator architectures and summarizes the primary advantages and disadvantages of each architectural family. In general, there are three primary degrees of freedom associated with the architectural selection for Σ∆ modulators: oversampling ratio (M), noise shaping order (L), and the modulator internal resolution (N), expressed in bits. Oversampling ratio is somewhat independent of the architecture. However, the noise shaping order (L) and the internal resolution (N) are intimately linked to the architecture. This section will provide an overview of the most common architectures and provide jus- tifications for the topology targeted in this research. Order 1&2 Advantages Inherently Stable Single-bit output Disadvantages Low order noise shaping Spectral tones Cascaded (MASH) Advantages Inherently Stable High order noise shaping Reduced spectral tones Disadvantages Matching of analog/digital difficult Dynamic range limitations Reduced noise shaping efficiency Multi-bit output Order > 2 Advantages High order noise shaping Single-bit output Reduced spectral tones Disadvantages Inherently Unstable Requires compensation Requires monitors/resets Single Loop Multi-bit Advantages Resolution increase ~ bit increase Disadvantages Nonlinearity Multi-bit output Figure 3.1 Σ∆ modulator architectural comparison. 29 3.1 Single Loop Modulators Σ∆ modulators began with the most straight-forward architecture -- a single loop. When implemented as a loop of noise-shaping order 1 or 2, the configuration is uncondi- tionally stable. Unconditional stability means a bounded input will produce a bounded output, regardless of initial conditions. However, low-order modulators ( ) provide very limited noise shaping and have been shown to produce undesired spectral tones that further reduce the obtainable effective resolution. For these reasons, higher-order loops ( ) have been developed that provide high-order noise shaping, reduce the spectral tones, and still provide a single-bit output. Minimum output data path width is desired to minimize the complexity and implementation size of the digital filter. However, single- loop topologies of order > 2 are only conditionally stable and require the addition of com- pensation and monitoring/reset functions to detect and provide control for recovering from an unstable state. The cascaded modulator or MASH (multi-stage noise-shaping) archi- tecture provides a method to realize high-order modulators (>2) that are inherently stable [120]. However, this topology has several limiting characteristics including reduced input dynamic range, reduced noise-shaping order due to element mismatch, and multi-bit out- put. Of these, the dominant resolution-limiting characteristic is integrator gain mismatch. Precise integrator gain is required to minimize integrator leakage and to obtain high-order noise shaping functions. This requirement results from the fact that both analog and digi- tal means are used to implement the noise-shaping function and therefore the gains must be matched very closely to obtain the desired result. Further resolution can be obtained in both single-loop and cascaded modulators by using a multi-bit comparator/DAC in the loop. This method, called multi-bit, provides a resolution increase that is approximately L 2≤ L 2> 30 equal to the increase in the internal resolution. However, multi-bit modulators have two primary disadvantages - increased modulator output data width and a high sensitivity to DAC non-linearity errors [127]. In addition to the configurations discussed in this section, a new topology called multi- rate has recently been the focus of much research and has specific applicability to high- rate data conversion associated with communications applications [32]. This topology is not particularly suitable for seismic applications since the architecture is intended to extend the dynamic range of high-bandwidth converters employing low oversampling ratios. 3.2 Cascaded Modulators Cascaded architectures provide an alternative to interpolative structures for obtaining high-order stable noise-shaping functions. These topologies are composed of two or more cascaded interpolative or single-loop modulator stages. Each interpolative stage has a 1st- or 2nd-order noise-shaping function, therefore ensuring stable operation. The quantization noise from each stage is fed as the input into the following stage and each modulator out- put is filtered and a single output is produced as the sum of the filter outputs. Proper selec- tion of the filter stages results in cancellation of the quantization noise of every stage but the last. The final stage quantization noise is shaped to the order of the overall modulator thus producing the desired noise-shaping order. The error cancellation filters are imple- mented as digital functions since the output of each of the modulator stages is a bit stream. However, as will be shown later, precise analog integrators are required to cancel the early stage quantization error and thus produce the desired overall noise shaping function. 31 The most simple cascaded architecture, a 1-1 cascade, is composed of 2 single-order loops (See Fig. 3.2). However, the 1-1 cascade is generally undesirable due to the low- order noise shaping efficiency, spectral tones, and increased sensitivity to gain mismatch. A more common topology that ideally provides a 4th-order noise shaping function is the 2- 2 cascade shown in Fig. 3.3 [142]. The remainder of this section will develop the z- domain expressions for the 2-2 cascade modulator including the associated digital noise cancellation function. For the 2-2 cascade modulator architecture, the output of the first 2nd-order modulator block is . (3.1) Similarly, the output of the second modulator block is given by (3.2) where . (3.3) Y1 z( ) g1 g1 ′ -----       z 2– X z( ) 1 z 1– –( ) 2 EQ1 z( )+ 1 z 1– g2 ′ g1 ′ g2 ----------- 2–       z 2– 2 g2 ′ g1 ′ g2 -----------–       + + -----------------------------------------------------------------------------------= Y2 z( ) 1 g3 ″ -----       z 2– X2 z( ) 1 z 1– –( ) 2 EQ2 z( )+ 1 z 1– g4 ′ g3 ″ g4 ----------- 2–       z 2– 2 g4 ′ g3 ″ g4 -----------–       + + -----------------------------------------------------------------------------------= X2 z( ) Y1 z( ) g3 g3 ′ –( ) g3EQ1 z( )–= 32 + I1(z) - + X(z) b1 a1 y1 + β + - b3 A/D D/A y2 I3(z) H1(z) H2(z)λ + Y(z) 1st Order 1st Stage 1st Order 2nd Stage Error Cancellation A/D D/A Figure 3.2 1-1 cascade modulator architecture. + I1(z) - + X(z) ++ - g1’ g2’ g1 g2 y1I2(z) H1(z) H2(z) + Y(z) 2nd Order 1st Stage Error Cancellation + I3(z) - + ++ - g3’’ g4’ g4 I4(z) 2nd Order 2nd Stage + g3 g3’ y2 +G1 EQ1(z) G2 + EQ2(z) - Figure 3.3 2-2 cascade modulator architecture. 33 Assuming the relationships , (3.4) and , (3.5) the expression for Y1(z) reduces to the ideal function for a 2nd-order modulator given as . (3.6) Likewise, if (3.7) and , (3.8) then the transfer function for Y2(z) reduces to . (3.9) The output of these two modulator loops are processed to produce the desired output func- tion for the 4th-order modulator: . (3.10) Here β is a scaling parameter defined by the fixed integrator gains: . (3.11) g2 ′ 2g1 ′ g2 = g1 g1 ′ = Y1 z( ) z 2– X z( ) 1 z 1– –( ) 2 EQ1 z( )+= g4 ′ 2g3 ″ g4= g1 g1 ′ = Y2 z( ) 1 g3 ″ -----       z 2– X2 z( ) 1 z 1– –( ) 2 EQ2 z( )+= Y z( ) z 4– X z( ) β 1 z 1– –( ) 4 EQ1 z( )+= β g3 ″ g1g2g3 -----------------= 34 3.3 Digital Noise Cancellation As previously described, the second loop of the 2-2 cascade is used to shape the quan- tization noise of the first loop. The outputs of both 2nd-order loops, Y1(z) and Y2(z), are input to the digital noise cancellation block that ideally produces the desired result -- an output signal composed only of a delayed version of the input signal and the 4th-order shaped quantization noise of the second loop (see Eqn. 3.10). The output of the noise can- cellation block is given by . (3.12) Substituting the desired form of the output for H2(z), solving for H1(z), and rearrang- ing into a different form to minimize function implementation results in the topology of Fig. 3.4 where (3.13) and . (3.14) Fig. 3.4 shows the basic block diagram of the noise cancellation circuitry. The constants d0 and d1 are defined using the integrator gain values: , (3.15) and . (3.16) Y z( ) Y1 z( )H1 z( ) Y2 z( )H2 z( )+= HN1 z( ) z 2– = HN2 z( ) 1 z 1– –( ) 2– = d0 1 g3′ g1g2g3( ) ----------------------–= d1 g3″ g1g2g3 -----------------= 35 A more detailed diagram showing specifics of the functions and required bit widths is found in Fig. 3.5. Note that all mathematical operations are performed using 2’s comple- ment arithmetic. The sign bit is not included in the bit widths shown in Fig. 3.5. Using the classical gain weights produces a slightly reduced overall dynamic range under ideal conditions, but shows improved dynamic range in the presence of integrator gain mismatch [127]. In addition, the classical gain weights produce a reduced-complex- ity modulator implementation. Using the classical gain weights given by Boser [13] ( , and ) results in d0=1 and d1=4. HN1(z)Y1(z) - d1 d0 Y2(z) HN2(z) Y(z) Figure 3.4 Digital noise cancellation for 2-2 cascade architecture. g3′ 0= g1 g1′ g2 g2′ g3 g3″ g4 g4′ 0.5= = = = = = = = 36 Figure 3.5 Digital noise cancellation diagram (data widths shown for d0=1 and d1=4). z-2Y1(z) Y2(z) Y(z) 1 1 d0 d1 - z-1 z-1- - 1-z-1 1 1 5 6 7 43 1 3 37 CHAPTER 4 REVIEW OF THE LITERATURE The application of Σ∆ modulation techniques to high-resolution data conversion is perhaps the single most investigated topic in integrated circuit design literature over the past decade. The method is well understood, and a mass of literature has been devoted to topology variations, sources of error, sensitivity analyses, performance simulation, target fabrication technology (CMOS, BiCMOS, Bipolar, SOS, SOI), circuit implementation specifics, and to numerous applications examples from low-speed, high-resolution instru- mentation associated with seismic and medical applications [2,88,110], to moderate-reso- lution, high-speed communications applications [17,91,183,187,193]. In this section an attempt is made to summarize this vast wealth of work, with a particular emphasis on addressing the application of this research - high-resolution, high-temperature data con- verters for seismic imaging. A compilation of representative work in the area of sigma delta modulation techniques from 1988 - 2001 is shown in Tables 4.1 and 4.2. Each table is devoted to a class of mod- ulator architectures and provides parameters needed to perform useful comparisons: mea- sured resolution, digital output rate (DOR), measured power consumption, fabrication process, supply voltage, oversampling ratio (OSR), and internal resolution. Table 4.1 summarizes the published single loop architectures while Table 4.2 details the cascaded architectures. Though this research is associated only with switched capacitor implemen- 38 Table 4.1: Published single-loop Σ∆ modulators from 1988-2001 (1estimated power). Reference Res. DOR Power Process Supply Architecture OSR Int. Res. FOM-w FOM-v FOM-t (bits) (S/s) (mW) (V) (bits) Boser88 14.5 11700 12 3µm CMOS 5 2nd-order 256 1 44.26 16.60 199.19 Nors89 14.4 80000 75 1.75µm CMOS 5 2nd-order 128 1 43.36 2.60 195.14 DelSig90 20.1 1000 125 3µm CMOS --- 4th-order 256 1 111.23 --- --- Brandt91a 16 50000 13.8 1µm CMOS 5 2nd-order 256 1 4.21 1.37 18.95 Eynde91 14 500000 160 1.5µm CMOS 5 4th-order 64 1 19.53 0.55 87.89 Riton91 16.7 48000 200 2µm CMOS 5 5th-order 64 1 39.14 0.88 176.12 Bert93 21 10 6 2µm CMOS 5 1st-order + PWM --- --- 286.10 214.58 1287.46 Kert94 20 800 50 3µm CMOS 10 4th-order 320 1 59.60 11.32 566.24 Mats94 9.3 384000 1.56 0.5µm CMOS 1 RC, swing supp --- 2-bit 6.44 2.07 3.22 Nadeem94 13.7 2000 0.94 2µm CMOS 5 3rd-order 250 1 35.32 169.07 158.93 Thom94 20 984 45 2µm CMOS 10 5th-order 3-level 43.61 9.21 414.32 Yam94 17.1 160 1.1 1.2µm CMOS 5 4th-order 205 1 48.94 200.21 220.23 Chen95 15.7 40000 67.5 1.2µm CMOS 5 2nd-order 64 3-bit 31.70 2.11 142.65 Mino95 11 200000 94 0.8µm CMOS 3 7th-order --- --- 229.49 6.10 573.73 Saue95 12 32000 1 1.5µm CMOS 2.3 3rd-order 16 1 7.63 13.73 13.73 Tan95a 10 19200 2 0.8µm CMOS 3.3 2nd-order, SI 128 1 101.73 142.42 284.83 Tan95b 10 15625 0.78 0.8µm CMOS 1.2 2nd-order, SI 64 1 48.75 43.75 34.13 Baird96 13.7 500000 58 1.2µm CMOS 5 4th-order 16 4-bit 8.72 0.68 39.22 Gril96 15.3 7000 2 0.6µm CMOS 1.8 2nd-order 285 1 7.08 4.60 9.21 Zwan96 13 8000 0.2 0.5µm CMOS 2.2 4th-order, cont. loop filt. 64 1 3.05 25.94 5.19 Au97 11.8 16000 0.34 1.2µm CMOS 1.95 3rd-order, local feedback 64 1 5.96 25.42 8.64 Leun971 19.6 44000 760 0.8µm CMOS 5 7th-order 140 3-level 21.74 0.13 97.81 Medeiro97a 16 20000 5.5 1.2µm CMOS 5 2nd-order 256 1 4.20 3.43 18.88 Medeiro97d 17.1 4800 1.71 0.7µm CMOS 5 2nd-order 512 1 2.54 6.67 11.41 Nys97 19 800 1.32 2µm CMOS 5 2nd-order 512 9-level 3.15 10.73 14.16 Peluso97 12 6800 0.1 0.7µm CMOS 1.5 2nd-order 74 1 3.59 35.90 3.59 Send97 14.3 20000 0.55 0.5µm CMOS 1.5 2nd-order, double sampling 50 1 1.36 2.48 1.36 Thanh97 13.4 195000 25.9 1.2µm CMOS 5 2nd-order 128 1 12.29 2.13 55.29 Zwan97 15.7 40000 2.3 0.8µm CMOS 3.3 4th-order, gm-C --- --- 0.62 0.76 1.74 Burger98 14 200000 2.8 0.5µm CMOS 3 3rd-order 48 1 0.85 0.76 2.14 Falak98 13.8 10000000 75 0.5µm CMOS 2.5 4th-order 12 6-bit 0.53 0.01 1.05 Ma98 14 14000 0.425 0.6µm CMOS 1 2nd-order 143 1 1.85 2.18 0.93 Marques98 14.8 2000000 230 1µm CMOS 5 4th-order 24 1 4.03 0.08 18.14 Peluso98 12.5 32000 0.04 0.5µm CMOS 0.9 3rd-order 48 1 0.22 2.16 0.09 Yasuda98 12.8 200000 9.6 0.6µm CMOS 2.7 3rd-order, dyn. el. match. 25 9-level 6.73 1.54 14.81 Coban99 16 40000 1 0.5µm CMOS 1.5 4th-order 64 1 0.38 0.38 0.38 Lin99 10.5 5000000 12 1.2µm CMOS 3 2nd-order, cont. time 16 1 1.66 0.35 4.14 Dess00 14.3 50000 1 0.35µm CMOS 1 3rd-order 100 1 0.99 0.50 0.50 Geerts00a 15.8 2500000 152 0.65µm CMOS 5 3rd-order 24 4-bit 1.07 0.03 4.80 Geerts00b 11.5 12500000 152 0.65µm CMOS 5 3rd-order 8 4-bit 4.20 0.12 18.89 Maulik00 15.3 500000 210 0.6µm CMOS 5 5th-order 64 1 10.41 0.22 46.85 Nagari00 11.7 270000 4 0.5µm CMOS 2.7 2nd-order, double sampling 48 1 4.45 2.45 9.80 Naik00 21.6 2000 21 0.6µm CMOS 3 4th-order 512 1 3.30 0.39 8.26 Thom00 18.3 240 41 --- 5 4th-order --- --- 529.33 58.10 2381.97 Dess01 14.3 50000 0.95 0.35µm CMOS 1 3rd-order 100 1 0.94 0.50 0.47 Fogle01 16.7 48000 70.4 0.5µm CMOS 3.3 2nd-order 64 33-level 13.78 0.55 38.57 Li01 12.2 6800 0.038 0.35µm CMOS 1.2 2nd-order, sig. adapt cntrl. 64 1 1.19 21.88 0.83 Snoeij01 16.7 22000 1.5 0.5µm CMOS 2.5 4th-order 64 1 0.64 0.85 1.28 39 tations, publications using other methods including switched current (SI) and continuous time (cont. time) are presented for completeness. Performance comparisons of Σ∆ modulators can be made using a figure of merit (FOM) that incorporates the three primary metrics of modulator performance: power con- sumption, effective resolution, and digital output rate (DOR). A common form given by Mediero97 [129] is . (4.1) Table 4.2: Published cascade Σ∆ modulators from 1988-2001 (1estimated power). Reference Res. DOR Power Process Supply Architecture OSR Int. Res. FOM-w FOM-v FOM-t (bits) (S/s) (mW) (V) (bits) Longo88 13 160000 20 1.5µm CMOS 5 2-1 Cascade 16 1 15.26 3.43 68.66 Brandt91b 12 2100000 41 1µm CMOS 5 2-1mb Cascade 24 1-3b 4.77 0.52 21.45 Yin93 15.7 320000 65 1.2µm CMOS 5 2-1 Cascade 64 1 3.82 0.26 17.17 Dedi94 14.7 200000 40 1.2µm CMOS 5 2-2-2mb Cascade 16 3-level 7.51 0.85 33.81 Will94 17 50000 47 1µm CMOS 5 2-1 Cascade 128 1 7.17 0.69 32.27 Yin94 16.5 1500000 180 2µm BiCMOS 5 2-1-1 Cascade 32 1 1.29 0.03 5.83 Chang951 12 1540000 250 0.7µm CMOS 5 2-1-1 Cascade 32 1 39.63 0.71 178.35 Rabii96 15 50000 5.4 1.2µm CMOS 1.8 2-1 Cascade 80 1 3.30 0.79 4.28 Medeiro97b 16.7 40000 10 1.2µm CMOS 5 2-2 Cascade 128 1 2.35 1.06 10.57 Medeiro97c 12.9 2200000 55 0.7µm CMOS 5 2-1-1mb Cascade 16 1-1-3b 3.27 0.27 14.72 Fuji97 18.2 48000 500 0.7µm CMOS 5 2-2mb Cascade 128 3-level 34.59 0.31 155.67 Rabii97 16.1 50000 2.5 0.8µm CMOS 1.8 2-1 Cascade 80 1 0.71 0.37 0.93 Feld98 12.5 1400000 81 0.72µm CMOS 3.3 2-2-2mb Cascade 16 1-1-3level 9.99 0.35 27.97 San98 15.3 64000 79 2µm CMOS 6.6 2-1-1-2 Cascade 16 1 30.60 2.36 186.65 Medeiro99 12.9 2200000 55 0.7µm CMOS 5 2-1-1mb Cascade 16 1-1-3b 3.27 0.27 14.72 Fuji00 16 2500000 165 0.5µm CMOS 5 2-1-1mb Cascade 8 4b-4b-4b 1.01 0.03 4.53 Gomez00 16.6 44100 13 0.6µm CMOS 3 2-1 Cascade 128 1 2.97 0.57 7.42 Moriz00a 12 2200000 109 0.35µm CMOS 3.3 2-2mb Cascade 24 1-5b 12.10 0.31 33.87 Moriz00b 13 2200000 165 0.35µm CMOS 3.3 2-2-2 Cascade 24 1-1-1 9.16 0.16 25.63 Oli01 13.7 360000 5 0.35µm CMOS 1.8 2-2 Cascade 36 1 1.04 0.27 1.36 Vleugels01 15.5 4000000 150 0.5µm CMOS 2.5 2-2-1mb Cascade 16 5b-3b-3b 0.81 0.01 1.62 Wang01 18.5 25000 75 0.6µm CMOS 5 2-2 Cascade 64 1 8.67 0.52 39.03 FOM w– Power W( ) 2 resolution bit( ) DOR S s⁄( )× ------------------------------------------------------------------ 10 12⋅= 40 However, many applications exist where other performance parameters are of interest such as supply voltage. An alternative FOM (FOM-v) has been defined for this research to emphasize supply voltage efficiency, resolution, and DOR, and is given as: (4.2) The numerator of FOM-v represents the useful dynamic range of the actual circuit imple- mentation. Thus, a 0.5 volt factor is subtracted to account for circuit dynamic range limi- tations in implementation associated with input stage current sources and output stage voltage swing limitations. An alternative form that includes all of the parameters of both FOM-w and FOM-v into account is shown below: (4.3) In Tables 4.1 & 4.2, all three forms of the FOM are provided for comparison and demon- strate similar performance for both single-loop and cascaded architectures. Note that for all FOMs, a lower value indicates improved performance relative to the metrics consid- ered. In terms of FOM-w, Peluso [152] produces the lowest value using a 3rd-order sin- gle-loop architecture operating with a 0.9V supply. Ignoring power consumption and considering supply efficiency, both Falakshahi [53] and Vleugels [196] produce a FOM-v of 0.01, using a 4th-order single-loop and a 5th-order cascaded architecture, respectively. Incorporating all metrics, including power and supply efficiency (FOM-t), Peluso [152] produces the best FOM result at 0.09. The extremely low-power consumption achieved in this design differentiates it from most published designs. FOM v– Vsupply 0.5– 2 resolution bit( ) DOR S s⁄( )× ------------------------------------------------------------------ 10 9⋅= FOM t– Vsupply 0.5–( ) Power W( )× 2 resolution bit( ) DOR S s⁄( )× ------------------------------------------------------------------------- 10 9⋅= 41 Further comparisons of the published designs of Table 4.1 and Table 4.2 are shown in Fig. 4.1 and Fig. 4.2. Fig. 4.1 shows the resolution-speed plane for both single-loop and cascaded architectures. Obviously, single-loop architectures have been published for a wide range of resolutions and speeds, and have shown the overall highest effective resolu- tion. Conversely, cascaded architectures are more tightly clustered and show on average better performance for high DOR, moderate-resolution applications. Fig. 4.2 shows the published work of Table 4.1 and Table 4.2 placed in the power- speed plane. Here the single loop architectures span the broadest area and produce the lowest power designs. In general, the cascaded architectures provide the highest DOR performance with similar power consumption to the single-loop designs. A more detailed discussion of both the single-loop and cascaded architectures and associated attributes is provided in following sections. Figure 4.1 Resolution vs. speed (published modulators 1988-2001). 8 10 12 14 16 18 20 22 1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Digital Output Rate (Samples/s) E ff ec ti ve R es o lu ti o n ( b it s) Cascade Single Loop 42 In addition to the BiCMOS and CMOS designs reported in research literature, a num- ber of designs have been published using alternative implementation techniques and alter- native target processes such as InGaP/InGaAs HEMT [148], SiGe HBT [74], and super- conducting fabrication methods [66,167,171] with sampling frequencies as high as 30 GHz. These designs, however, are directed towards very high-speed conversion and therefore offer poor resolution. The most promising fabrication technologies suitable for general high-temperature implementation are Silicon-on-Insulator (SOI) and Silicon-on-Sapphire (SOS) [39,60,61,64,65,67,76]. Only a few publications reporting the use of SOI/SOS for modu- lator implementation exist, targeting three specific application areas: high-temperature [198,199], low-voltage low-power [181], and radiation tolerant data converters [45]. Viv- iani [198,199] reports 1st- and 2nd-order modulator designs, respectively, in fully-depleted Figure 4.2 Power efficiency vs. speed (published modulators 1988-2001). 1.0E-09 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Digital Output Rate (Samples/s) P o w er (W )/ 2^ b it Cascade Single Loop 43 SOI CMOS with measurement results up to 350 C. [199] provides the most promising data in terms of high-temperature performance reporting 9-bit resolution at 300 C using a 2nd-order modulator. The specifics of these designs are shown in Table 4.3. These refer- ences show progress regarding the implementation of sigma delta structures in SOI/SOS processes, but implement only low-order, low-resolution modulator designs. As demonstrated, the area of Σ∆ modulation continues to be a popular research topic, with most current research being directed towards high-speed moderate-resolution designs suitable for RF system application. The majority of the published work uses standard CMOS fabrication technologies following the electronic industry’s move to smaller fea- ture size, lower supply voltage processes. This work continues to progress and has shown impressive improvement for standard temperature applications. A small number of SOI or SOS designs have been published using low-order modulator architectures to obtain low- resolution results for both high-temperature and high-radiation environment applications. In addition, much work has been reported showing applicability of SOI/SOS to low-volt- age low-power applications. The goal of this research is to address this missing compo- nent of high-temperature converters by demonstrating the first high-resolution, high- temperature modulator suitable for extreme environment applications. Successful demon- ° ° Table 4.3: Published SOS/SOI Σ∆ modulators from 1988-2001. (*indicates peak SNR). Reference T Resolution DOR Power Process / Supply Architecture OSR Internal (C) (bits) (S/s) (mW) Resolution Viviani96 27 9.3* 781 0.06 3µm SOI-CMOS / 2V 1st order 128 1-bit 350 4.7* 3906 0.5 3µm SOI-CMOS / 2V 1st order 128 1-bit Viviani99 30 11 15625 --- SOI-CMOS / 5V 2nd order 64 1-bit 250 10 15625 --- SOI-CMOS / 5V 2nd order 64 1-bit 300 9 15625 --- SOI-CMOS / 5V 2nd order 64 1-bit Swaminathan99 27 8* 400000 0.3 0.25µm SOI-CMOS / 1V 2nd order 125 1-bit Edwards99 27 9.7 126000 --- 1.5µm SOS-CMOS / 5V 1st order 128 4-bit 44 stration of this design will extend the application of sigma delta modulation techniques to a variety of applications currently inaccessible to conventional designs. Recent published literature in the area of high-temperature data conversion has dem- onstrated potential application of Σ∆ architectures to the specialized field of high-resolu- tion seismic imaging. The use of silicon-on-sapphire (SOS) and silicon-on-insulator (SOI) processes are commonly employed to elevated temperature applications for reasons previously discussed. However, all reported topologies designed and tested for high-tem- perature application to date have been single-loop architectures of order 2 or less. These reported developments produce at best 11 bits of resolution at typical seismic temperatures (160 C) falling way short of the resolution needed for the demanding dynamic range requirements of seismic imaging (16-24 bits). Clearly, the research community has not adequately addressed the problem of high-resolution data conversion at elevated tempera- tures. The primary objective of this research is to demonstrate the first high-resolution Σ∆ modulator capable of 16-18 bit performance at elevated temperatures exceeding 160 C. As a result of this research several specific contributions to the area of sigma delta modulator design for high temperature applications are evident. First, this work reports the first 4th-order modulator in an SOS or SOI process and provides the first comparison of 2nd- and 4th-order cascaded modulators in a high-temperature process. Additionally, this work presents a thorough description of the modulator test system providing detail on the associated hardware, software, and general testing approach. Finally, this research presents a comprehensive and well organized suite of modulator test results as a function of temperature - a more complete presentation of data than previously detailed in litera- ture. ° ° 45 CHAPTER 5 MODULATOR DESIGN & SIMULATION This chapter presents a thorough summary of the design of the modulator. The demanding temperature requirements of the target application emphasize the need for spe- cial attention in the selection of the modulator design parameters. Many of the design decisions that are acceptable for room temperature designs do not apply in the case of down-hole seismic. Consequently, many conservative decisions are outlined in the fol- lowing text that ensure stable operation over a wide temperature range, at the cost of reduced room temperature performance. 5.1 Modulator Architectural Selection As previously mentioned, the two primary design requirements for down-hole seismic digitizers are maximum dynamic range and stability over a wide range of temperatures. Though high-order single-loop modulators with multi-bit internal resolution are capable of the best performance in terms of dynamic range (or effective resolution), there are many opportunities for problems associated with component temperature dependencies. Electronics placed down-hole are not only subjected to extremely high temperatures, but also experience wide swings in temperature, especially during deployment. Additionally, the static operating temperature each of the data collection nodes is subjected to depends largely on geothermal gradients, such that the nodes at either end of the string experience large environmental temperature differences. For these reasons, the cascaded architecture 46 was selected since unconditional stability is ensured by this topology. Though single-loop high-order modulators ( ) offer some advantages, they are at best conditionally stable when appropriate compensation is incorporated. In addition to simplified compensation, cascaded architectures do not require the integrator initialization and monitoring functions that are required in the high-order single-loop topologies to ensure stability. A properly designed cascaded modulator can provide increased robustness over high-order single- loop architectures, particularly over a wide temperature range, at the acceptable cost of slightly reduced resolution. Regardless of the loop architecture, the design of the any modulator begins by selec- tion of the three primary design parameters: noise shaping order (L), oversampling ratio (M) and internal resolution (N). Preliminary performance modeling of a modulator as a function of L, M, and N was performed using MATLAB [119] using Eqn. 5.1 and Eqn. 5.2, repeated below for convenience. Fig. 5.1 shows the theoretical resolution for realiz- able values of L and M with N=1. Table 5.1 summarizes the maximum achievable resolu- tion from selected points on these curves. (5.1) (5.2) The performance goal of this design is to match the 24-bit intrinsic resolution specifi- cation published for commercial seismic-grade Σ∆ converters. Theoretically, meeting this goal requires the use of a 3rd-order modulator with M=256. Use of this oversampling ratio L 2≥ DR 3 2 --- 2L 1+ π2L ----------------    M 2L 1+( ) 2 n 1–( ) 2 = B bit( ) 1 2 ---log2 2 n 1–( ) 2 2L 1+( ) M 2L 1+( ) π2L -----------------------------------------------------------------       = 47 Table 5.1: Theoretical resolution as a function of M and L (N=1). Modulator Order M=64 M=128 M=256 M=512 1 8.14 9.64 11.14 12.64 2 12.86 15.36 17.86 20.36 3 17.45 20.95 24.45 27.95 4 21.98 26.48 30.98 35.48 5 26.47 31.97 37.47 42.97 10 1 10 2 10 3 5 10 15 20 25 30 35 40 Oversampling Ratio (M) R es ol ut io n [b its ] L=2 L=3 L=1 16 bits 24 bits L=4 M=256 M=512 Figure 5.1 Theoretical modulator resolution vs. L and M for N=1. 48 provides a significant improvement in SNR due to oversampling, while allowing a reason- able settling time for the target sampling frequency of 512 kHz. Note that the calculations used to predict the required L and M are ideal -- the errors associated with an imperfect noise shaping transfer function, input-referred electronic noise, and distortion are omitted. In practice these factors, unaccounted for in these calculations, will ultimately limit the effective resolution of the converter. These sources of error are addressed in later sections of this chapter. The internal resolution of the modulator (N) was chosen to be 1 bit. Increasing the internal resolution of the modulator from 1 bit using multi-level quantization and error feedback produces roughly the same increase in modulator resolution. However, very pre- cise implementation of the multi-level quantizer and feedback DACs is required or the effective resolution may actually be reduced. For example, in a 2-2 cascade with 3-bit quantization, a non-linearity of 1mLSB causes a 25% reduction in SNR [127]. This is the result of the DAC output being summed at the input of the loop. Due to the difficulty of achieving high linearity over a wide temperature range, a multi-bit architecture was not used in this design, but may be considered for future work. The use of 1-bit quantization ensures linearity. A 2-2 cascade architecture was chosen for the realization of the modulator due prima- rily to its inherent unconditional stability. Though there are some slight performance pen- alties for using a cascaded modulator, the issue of stability over a wide-temperature range is of paramount importance. The primary disadvantages include sensitivity to mismatch of analog and digital gain coefficients, dynamic range penalties, and increased output bit width. For actual implementation, a 4th-order noise shaping transfer function was chosen 49 for several reasons. First, the quantization noise spectral density is not actually uniform so the SNR calculations performed are optimistic [81,159]. Using a 4th-order modulator will further shape the quantization noise to better suppress the expected spectral tones. In addition, a 2-2 cascade requires nearly the same design and ASIC layout effort as a 2-1 cascade since many of the individual circuit blocks are identical - a similar 2nd-order loop can be used for both loops in the cascade. A 2nd-order first stage was chosen since the lit- erature suggests that a 2nd-order first stage produces a more robust system than a 1st-order first stage [163]. The primary disadvantage of this approach (choosing a 2-2 cascade over a 2-1 cascade) is the increased output data stream bit width from the modulator which increases the complexity and size of the digital filter [142]. Having selected a modulator topology and associated parameters L, M, and N, the integrator gains need to be determined. The integrator gain selection issue can be rather complex because closed form modeling of higher-order modulators is extremely difficult. As a result, the majority of published literature uses simulation or empirical means for gain determination [127,207]. Considering the design complexity issues and sensitivity to gain mismatch errors, the classical gain selection presented by Boser provides the best overall solution for this design [13]. This selection of gains has been shown to minimize the design complexity of the modulator, and provide decreased sensitivity to gain mis- match errors compared to gain selections maximizing the use of available circuit dynamic range [127]. Tolerance of gain mismatch is an especially important attribute in designs that have to operate over wide temperature ranges. The final 2-2c cascade architecture selected for implementation is shown in Fig. 5.2. Using the classical gain settings, and all other gain values are set to 0.5. Theg3 ′ 0= 50 noise cancellation circuitry is completely digital. Since the architecture is composed of two separate 2nd-order loops, measurement and analysis of both a 2nd- and 4th-order mod- ulator is possible from the same design. This ability to configure the modulator as both a 2nd- and 4th-order modulator provides the flexibility required for thorough evaluation of the design techniques, selected architecture, and performance of the modulator in the tar- get temperature-tolerant integrated circuit technology. The selection of integrator gains for achieving a specific noise shaping function for a given modulator topology affect the selection and design of several other modulator parameters: the integrator opamp output swing, the feedback voltage levels supplied by the DACs, and ultimately the modulator input dynamic range. The integrator opamp out- put swing is the limiting factor and is determined first and then used to calculate the other Figure 5.2 2-2 cascade modulator topology selected for implementation. + I1(z) - + X ++ - g1’ g2’ g1 g2 A/D D/A y1I2(z) H1(z) H2(z) + Y(z) 2nd-Order Loop 1 Error Cancellation + I3(z) - + ++ - g3’’ g4’ g4 D/A I4(z) 2nd-Order Loop 2 + g3 g3’ y2A/D 51 parameters. When using cascaded architectures, these levels must be selected to prevent input overloading of the second loop. For the 2-2c topology used in this research, the rela- tionships between the opamp output swing (OS), the maximum input amplitude (Vin), and the feedback reference voltages (Vref) are given as [127] . (5.3) Determination of the maximum integrator opamp output swing is a function of the circuit design and is covered in detail in following sections. A qualitative verification of the selected topology and associated gains was performed using a Unix-based switched circuit simulator developed at Stanford University called MIDAS [130]. Fig. 5.3 shows the output produced from simulation of the 2-2c cascade modulator for both 2nd-order loops and for the overall 4th-order transfer function produced by the digital noise cancellation circuitry. The results of these simulations verified that the modulator architecture was reasonably constructed, including both modulator loops and associated gains, and the digital noise cancellation circuitry. The expected 40dB/decade and 80dB/decade slopes were observed for the 2nd- and 4th-order modulators, respectively. The spreading of the fundamental is both the result of windowing and limited FFT resolu- tion. In addition to spectral plots of the modulator output, the outputs of each of the inte- grators were monitored to ensure stable operation with a full-scale single tone input. These simulations are ideal in that only the quantization noise is modeled in the simula- tion. A discussion of the additional noise sources present in practical modulator imple- mentation and methods for reducing the associated adverse effects on modulator performance are addressed in following sections. Vin V≤ ref OS( ) 2⁄≤ 52 5.2 Modulator Noise Analysis There are a number of noise sources that limit the performance of a Σ∆ modulator: namely, modulator quantization noise and the electronics noise associated with the inte- grator opamp, comparator, and integrator switches. If sufficient modulator noise shaping order is employed, the quantization noise is reduced sufficiently in the input signal fre- quency bandwidth causing the sources of electronic noise to become the primary limiting factor. This input-referred noise power spectral density is composed of two primary sources, white noise and 1/f or flicker noise, and can be expressed as (5.4) Figure 5.3 MIDAS simulation results for the 2-2c modulator architecture with full-scale, 100Hz single tone input. -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Frequency [Hz] F F T M ag n it u d e [d B ] 2nd Order (Loop 1 Output) 4th Order (DNC Output) Loop 2 Output ξ f( ) ξw K f ----+= 53 Here represents the white noise and K is a constant associated with the 1/f noise. The development of the expressions in the remaining parts of this section closely follow the published work of Williams [207]. A common phenomenon in modulators that must be carefully considered in the