A study of frequency-sampling filters realized on floating-point digital signal processors

This thesis deals with finite impulse response (FIR) digital filters implemented in floating-point arithmetic using the frequency-sampling structure. Ideally the poles and zeroes fall on the unit circle, but to avoid stability problems they must be moved slightly inside, degrading the frequency response desired. This research examines the effect on the frequency response produced by moving the poles and zeros inside the unit circle. The farther they are moved inside, the lower the roundoff noise becomes. This work determines the radius values where the roundoff noise is comparable to that of the direct convolution realization, while still retaining an acceptable frequency response. It also determines whether the frequency-sampling realization is superior to the direct convolution sum in terms of processing time on a typical floating-point digital signal processor, (the Motorola DSP96002). It is found that the frequency-sampling realization is much more efficient for narrow-band filters.

The frequency-sampling realization is a viable method of realizing FIR digital filters on a floating-point digital signal processor. When the radius is between 1 2^-9; and 1 2^-12; the frequency response of the frequency-sampling filter is acceptable and the roundoff noise is slightly greater but comparable to the direct convolution method. The efficiency of implementation in terms of real processing time is shown to be much better than that of the direct convolution sum method for narrow-band filters with stopbands less than π/2.7.