CMOS-Memristive Neuromorphic Architecture for Nonlinear Signal Processing

Neuromorphic computing mimics the functional components and structure of the human brain to achieve highly efficient computing with minimal resources and power consumption. Creating neuromorphic systems in Complementary Metal-Oxide-Semiconductor (CMOS) technology offers an alternative computing paradigm to Von neumann computing. However, implementing these systems on an CMOS Integrated Circuit (IC) poses major challenges. These challenges include implementing synaptic weight multiplication and weight tuning operation that conserves energy and occupies minimal area. Additionally, designing a network-on-chip architecture that is reconfigurable and offers a full-connectivity design space is crucial. Furthermore, implementing a complete architecture for nonlinear data processing and, specifically, online learning on-chip is another significant challenge. Memristors are emerging nano devices that exhibit behavior similar to synapse in the brain with few of the memristor types offering extremely small footprint and non-volatile resistance on-chip. These properties lead to small area and low-power IC designs. The device models for these emerging devices are crucial for designing circuits and systems that utilize them. In this work, we address the integration of memristors with the circuit simulation environment by modeling crucial features of these devices in a SPICE-compatible model. The presented model offers a very low 2-3% error in LRS tuning when compared to average experimental data while converging well in simulation. Further, we also present a reconfigurable and scalable network architecture that allows full connectivity while minimizing resource overhead for spike communication between proximal neurons by ensuring "spikes-as-spikes" communication. For spike communication between neurons farther away on-chip from each other, AER is utilized. Thus, a Hierarchical Circuit-Packet Hybrid approach for scalable neuromorphic systems is proposed. This technique leads to up to 48% savings in area and 90% savings in power for the neurons placed physically close to each other on-chip. Lastly, we present resource-efficient hardware architecture for online learning using the reservoir computing approach for non-linear signal processing. The application of wireless channel equalization is considered which includes reflection, inter-symbol interference, and signal attenuation and also has a memoryless non-linearity of a second order. The proposed approach leverages the circuit-switched Network-on-Chip (NoC), SpiCS-Net, as a robust "spikes-as-spikes" routing mechanism for handling input and output spikes within the reservoir. This strategy enables resource optimization by strategically reducing the number of output neurons, while simultaneously preserving the system’s flexibility to designate any neuron within the reservoir as an output neuron. The proposed approach offers upto 30% savings in area of the output layer in IBM CMOS10LPE 65 nm technology.