An investigation of different mincroprocessor-based organizations for systems generating histograms

This thesis investigated the limitations of different microprocessor-based organizations for systems generating Time (interval and dwell) and amplitude histograms. Applying successive design techniques on the existing hardware developed an optimal architecture for the interval histogram processor. The same architecture was utilized to generate dwell and amplitude histograms. Analysis on the above processors revealed that architectures for histogram systems were best obtained by using multiprocessing and software minimization. The Interval processor was built by laboratory kits to demonstrate the feasibility of multiprocessing.