Studies on high-speed analog memories for physics experiments with emphasis on radiation hardening

The use of analog memory units (AMUs) for fast storage in large physics experiments has grown dramatically in the last five years. As more experiments require improvements in measurement precision, the need for precise, fast, small and low-priced temporary data storage has increased to where almost every major experiment has at least one subsystem with imbedded analog memory. Along with the increased usage has come increased expectations of the performance of such memories. The newer high-energy experiments such as the now-defunct Superconducting Super Collider (SSC) and the Large Hadron Collider at CERN in Switzerland require memories that are resistant to ionizing radiation and heavy particles. This thesis presents the development and testing of such memories. Two different memory topologies as well as two different readout amplifiers were designed, fabricated in a radiation-hard CMOS process (Harris AVLSI-RA), and tested. Combinations of these circuits were tested for linearity, pedestal variation, cell droop (leakage), and nearest neighbor interaction. The circuits were tested after exposure to 0-, 1-, and SMRad of gamma radiation. The results indicated that the CMOS process was radiation-hard to at least SMRad ionizing radiation. The Voltage-Write-Voltage-Read (VWVR) topology exhibited better linearity, pedestal performance, and less effect on nearest neighbors than the Voltage-Write-Charge-Read (VWCR) topology. A method of pedestal correction used with a memory fabricated in a non-rad-hard process was also tested that indicated address-dependent pedestal noise (so called 'pattern' noise) could be reduced by employing a real-time correction. Radiation levels of up to 75KRad in a standard process had no effect on the correction method.