Physics based modeling of multiple gate transistors on Silicon-on-Insulator (SOI)

G⁴FET is a novel device built on Silicon-on-Isulator (SOI). Due to the presence of Bulk-Si, it is impossible to have more than one gate for each transistor in conventional process technology. However, it is possible to have multiple gates for each transistor in SOI devices due to the presence of buried oxide, which can be used as an independent gate. Besides the oxide gates, junction gates can also be introduced. Due to the presence of the thin active layer, the junction gate can reach to the bottom and can be used to isolate and control the conduction in the transistors. As a result, the maximum number of gates that can be achieved in SOI is four. A transistor with four gates is called G⁴FET. G⁴FET offers all the features of SOI technology. It offers remedies of the drawbacks of Bulk-Si technology. The operation of the multiple gates has applications for mixed-signal circuits, quantum wire, and single transistor multiple gates logic schemes, etc. The research goal is to understand the device physics of G⁴FET. Understanding device physics will provide enough information to set device parameters to optimize device performances. The operation of semiconductor devices depends on several material parameters, device dimensions and structure. The objective of this research is to develop a model that includes material parameters, device dimensions and structure. The second objective of this research is to develop a numerical model from available data. The numerical model is useful for circuit simulation of G⁴FET, which provides information about the characteristics of G⁴FET, when used as a circuit element.