Path-constrained and incremental floorplanning using sequence pairs

This research focuses on the floorplanning stage of the VLSI physical design cycle. The first part of this research is on path-constrained floorplan. In order to maximize CPU performance and improve clock cycle time, modules on critical paths must be placed in a straight line from an input pin to an output pin. This technique uses the sequence-pairs method. The second part of this research is on incremental floorplan. Given a floorplan, we want to generate a different floorplan that is very similar to the original floorplan after incremented changes in module sizes have been made. Once again, we use sequence-pairs with various cost functions to solve the problem. We have been successful in obtaining a provably correct solution for a limited version of the path-constrained problem. Experimental results demonstrating the efficiency of our methods are also presented.