A low dead time variable CMOS delay for the nuclear weapons identification system

The architecture and performance of a new CMOS based, low dead time, variable delay is described. This delay was developed to provide capability for channel synchronization in the Nuclear Weapons Identification System (NWIS) front­end electronics ASIC. The delay is variable over a 500ns range in smaller than 100ps steps. Low dead time is achieved by using a switched parallel channel architecture. The delay channels are feedback stabilized using a phase locked loop (PLL) locked to a crystal reference. A prototype has been fabricated in the 1.2u AMI process and tested to evaluate its performance.