A PLL frequency synthesizer for a 300 MHz high temperature transceiver realized in 0.5um SOS technology

This thesis presents a study of the design of a phase-lock loop (PLL) system, including specific designs for a voltage-controlled oscillator and programmable frequency divider, implemented in a 0.5μm silicon-on-sapphire CMOS technology. The system is designed for use as a frequency synthesizer in a high-temperature transceiver. Several issues relating to high-temperature applications as well as the overall system architecture are presented. Principles of the PLL system are described, and critical design considerations are discussed. The designs of the VCO and programmable divider are described and analyzed in detail. A brief discussion of the design and analysis of other PLL components is presented. Prototyping and testing procedures are discussed and the results of the prototyped circuits are evaluated. Finally, a summary of the work is presented along with insights gained toward future research.