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A SiGe BiCMOS LVDS Driver for Space-Borne Applications

Date Issued
December 1, 2013
Author(s)
Laurence, Matthew Ian  
Advisor(s)
Benjamin J. Blalock
Additional Advisor(s)
Chuck Britton, Syed Islam
Abstract

When designing an integrated circuit for use during an interstellar mission, certain precautions must be made. The electronics on any off-earth mission will be exposed to wide temperature swings and harmful radiation due to being outside of the Earth’s protective ionosphere. It is crucial that any data path present be immune to these detrimental effects.


The introduction of galactic radiation can not only cause the onboard electronics to fail due to device degradation and single event latchup but can also lead to background radiation being coupled into the signal path as unwanted noise, degrading the signal to noise ratio. Unwanted noise can cause total failure by increasing the noise level and decreasing the signal to noise ratio below one or can cause errors such as single event upsets.

The wide temperature swing can cause device degradation and eventually failure. This issue is commonly mitigated by the introduction of an environment chamber but such an enclosure adds unnecessary mass and typically requires a large amount of current to effectively keep the electronics in an Earth-like temperature. The large current implies high power dissipation which is an unnecessary strain on the battery and can shorten the lifetime of a mission where every kilowatt-hour is crucial to success.

The solution to these two non-trivial obstacles is to design an electronic circuit such that it can operate in a wide range of temperatures and can withstand the galactic radiation that it will inevitably encounter during its mission’s lifetime. The following thesis will document the design, simulation, and testing of a Si-Ge Bi-CMOS low voltage differential signal driver for space borne applications.

Subjects

SiGe

BiCMOS

LVDS

Space

Disciplines
Electrical and Electronics
Electronic Devices and Semiconductor Manufacturing
Degree
Master of Science
Major
Electrical Engineering
Embargo Date
January 1, 2011
File(s)
Thumbnail Image
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MIL_THESIS_REV_4.doc

Size

10.44 MB

Format

Microsoft Word

Checksum (MD5)

7f2d6534cef97323fbd056d21c5ce930

Thumbnail Image
Name

MLaurenceFinal.pdf

Size

3.18 MB

Format

Adobe PDF

Checksum (MD5)

2dde3b2ad96dcbd09df598a5d49e51b4

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