Development and evaluation of various scan-path storage cells

With the increasing complexity of VLSI design, testing the manufactured product with reduced time, cost and increased reliability has become a major criterion. Various scan techniques have evolved in response to such testing methodologies. The research reported here consists of the development and evaluation of several storage cells that can be used to support scan-path designs. Different soft-macro cells which include a multiplexed data shift-register latch, a two-port shift-register latch, a raceless two-port storage flip-flop, and a transmission gate based storage flip flop were mapped into silicon. The transmission gate storage cell's physical layout was also done manually as a leafcell in two layout formats. The leafcells were fabricated on a single CMOS 2 μm application-specific integrated circuit. Two-phase and pseudo-four-phase clocking schemes were studied. An evaluation of the suitability of the different cells for scan-path applications was then made. The six different leafcells may be incorporated into the library of cells for future designs. The two different manual leafcells areas are smaller than soft-macro version and are 42% and 56% of those of soft-macro version.