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  5. Design and Evaluation of a Sub-1-Volt Read Flash Memory in a Standard 130 Nanometer CMOS Process
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Design and Evaluation of a Sub-1-Volt Read Flash Memory in a Standard 130 Nanometer CMOS Process

Date Issued
December 1, 2017
Author(s)
Basford, David Andrew  
Advisor(s)
Jeremy Holleman
Additional Advisor(s)
Benjamin Blalock
Syed Islam
Permanent URI
https://trace.tennessee.edu/handle/20.500.14382/41132
Abstract

Nonvolatile memory design is a discipline that employs digital and analog circuit design techniques and requires knowledge of semiconductor physics and quantum mechanics. Methods for programming and erasing memory are discussed here, and simulation models are provided for Impact Hot Electron Injection (IHEI), Fowler-Nordheim (FN) tunneling, and direct tunneling. Extensive testing of analog memory cells was used to derive a set of equations that describe the oating-gate characteristics. Measurements of charge retention also revealed several leakage mechanisms, and methods for mitigating leakage are presented.


Fabrication of ash memory in a standard CMOS process presents significant design challenges. The absence of multiple polysilicon layers requires that additional devices be used to control the oating-gate voltage. Furthermore high-voltage devices are often required to isolate the selected memory cells during write and erase cycles. However, a single-poly design allows portability to another standard process provided that the oating-gate characteristics are known.

A ash memory system is presented here that has been fabricated in a standard 130 nanometer CMOS process. The design utilizes capacitive feedback to maintain desired injection current during programming. It also includes a sense amplifier design which features auto-zeroing of inherent offsets. Comparisons to existing memory designs show that a significant improvement in areal density was achieved through the elimination of on-die high-voltage charge pumps and switches. Measurements were performed over a range of clock frequencies and supply voltages. Results show that this memory system is capable of a read access time of 3.5 microseconds with a 1 megahertz clock while consuming less than 25 microwatts from a 1 volt supply. Operation down to 650 millivolts was confirmed where power consumption was reduced to only 3.4 microwatts. The low power consumption and high density of this ash memory make it an excellent choice for on-die firmware storage in battery-powered embedded applications.

Subjects

flash memory

VLSI

low-power

CMOS

single-polysilicon

floating gate

Disciplines
VLSI and Circuits, Embedded and Hardware Systems
Degree
Master of Science
Major
Electrical Engineering
Embargo Date
January 1, 2011
File(s)
Thumbnail Image
Name

thesis.pdf

Size

4.7 MB

Format

Adobe PDF

Checksum (MD5)

a6469dcf12b3c9a21cdef1a4a69490de


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