Development and Verification of Parameterized Digital Signal Processing Macros for Microelectronic Systems

Digital system design is a broad field that is growing every day. As technology grows, the complexity of systems grows also, which leads to longer design times. A Design-for-reuse policy can decrease design time by building flexibility into designs as they are created. By creating parameterized macros, they are more likely to be reused. Verifying the capabilities of macros is also important, and testing should be incorporated into each step of the design process. In this thesis, designing parameterized macros is discussed, with a Complex Fast Fourier Transform presented as an example of a complex algorithm, and three different Rounder blocks as examples of simple macros. Each Rounder was tested successfully, instantiating one of the Rounders with several different configurations. The Fast Fourier Transform macro was simulated successfully to Post-layout Simulation for one set of parameters, and for several sets was simulated in the Pre-synthesis step. The Fast Fourier Transform macro was fabricated using a TSMC 180nm process and verified to be working correctly.