Implementation of Wavelet Transform and Area, Power and Delay Design Space Exploration

The need for designing chips that are smaller, faster and less power consuming has been increasing, as these chips are increasingly being used in communication and portable electronic devices. These design space vectors also play a big role in the profitability and productivity of the vendor and hence prove to be one of the most important steps in the Application Specific Integrated Circuit (ASIC) flow (design process). The research reported here consists of implementing the Wavelet Transform using a hardware description language (VHDL) and testing the Register Transfer Level (RTL) for its functionality. The RTL was synthesized and optimized using the Synopsys Design Analyzer for multiple values of area, power and delay. Design constraints were setup in the tool to do this before the layout stage. The synthesized netlist was then placed and routed using EPOCH, which optimizes the area, power and delay of the ASIC at the post layout stage. Thus, fifteen different ASICs over a range of area, power and delay values were produced.