A study of zero-input limit cycles in floating-point digital signal processors

An experimental analysis of zero-input limit cycles in stable, second-order infinite impulse response filters with complex-conjugate poles implemented on the Texas Instruments TMS320C31 floating-point digital signal processor was performed. Results presented are based on studies using three second-order filter realizations. Limit cycle behavior was experimentally observed by moving transfer function poles across a dense grid within the unit circle in the z-plane, providing a complete study for the Direct Form, Minimum Roundoff Noise and Type in realizations. Limit cycles were found to be negligibly small for all three realizations, and their existence was found to be dependent upon the filter realization and the locations of the poles. In all three realizations, higher-Q filters (with pole radii close to the unit circle) were found to be more susceptible to limit cycles than lower-Q filters. Although transfer function poles were moved out to radii of 0.9999 for each filter realization, limit cycle magnitudes remained very small (around 10^-37). Cases involving rounding, truncation and magnitude-truncation of the state variables were investigated. The results were found to be virtually identical for all three indicating another source of the limit cycles. A detailed analysis of the effects of the processor's underflow flush-to-zero characteristic was performed. Deviations from the expected behavior of the filter were found to be correlated with instances where, while updating the state variables, the results of one or more calculations were "flushed" to zero. This final result suggests that the underflow flush-to-zero characteristic of the processor is the primary cause of the observed limit cycles.