Fundamental Limit of Analog Multiplication in Linear Discriminant Classifier

In this thesis analog implementation of a machine learning algorithm, Linear Discriminant Analysis, is analyzed and shown how it performs on a classification problem. Analog machine learning has emerged as a promising field that provides advantages over its digital counterpart in power consumption, circuit area and scalability. Analog computation achieves its efficiency from the physics of device or circuit operation. This allows analog computation to operate on very low signal levels. However, low signal levels make itself vulnerable to noise. Excessive noise levels can render the machine learning system unstable and prone to making wrong decisions. To ensure reasonable accuracy of the system it is essential to understand how noise behaves and propagates along the system.A key component in analog implementation of the Linear Discriminant Analysis is the analog multiplier. A noise analysis is done for the multiplier to show how noise varies with multiplication factor. This also produces a relationship between signal to noise ratio and energy consumption that gives us a limit of accuracy obtained from the multiplier for a given energy consumption. Numerical analysis is provided to show that Linear Discriminant Analysis is well suited for the classification problem. The performance of a hardware implementation of the analog classifier in commercially available 130nm silicon process is also presented. With four feature input currents and three classes to classify the classifier consumes around 4nW of power. The testing process shows that the classifier is able to perform basic classification task in the presence of noise.