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  5. Gate Drive Design for Paralleled SiC MOSFETs in High Power Voltage Source Converters
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Gate Drive Design for Paralleled SiC MOSFETs in High Power Voltage Source Converters

Date Issued
August 11, 2018
Author(s)
Timms, Craig
Advisor(s)
Fei Wang
Additional Advisor(s)
Benjamin J. Blalock
Daniel J. Costinett
Permanent URI
https://trace.tennessee.edu/handle/20.500.14382/41381
Abstract

High power voltage source converters (VSC) are vital in applications ranging from industrial motor drives to renewable energy systems and electrified transportation. In order to achieve high power the semiconductor devices used in a VSC need to be paralleled, making the gate drive design complicated. The silicon carbide (SiC) MOSFET brings much benefit over similarly rated silicon (Si) devices but further complicates the gate drive design in a parallel environment due to it’s fast switching capability and limited short-circuit withstand time. A gate driver design with proper accommodation of key issues for paralleled 1.7 kV SiC MOSFETs in high power VSC applications is developed.Three of the main issues are current imbalance, short-circuit protection, and cross-talk. By characterizing devices and supporting circuitry an understanding of constraints and sensitivities with regards to current balance between devices is developed for design optimization. A short-circuit detection scheme with adequate response time is employed and mitigation steps presented for issues arising from paralleling devices including large transient energy and instability. Cdv/dt induced gate voltage—cross-talk—is addressed by adapting a mitigation method to multiple devices. Finally, the gate driver is demonstrated in a full scale half-bridge using four devices per switch.

Subjects

SiC

Degree
Master of Science
Major
Electrical Engineering
File(s)
Thumbnail Image
Name

utkirtd_642.pdf

Size

3.66 MB

Format

Adobe PDF

Checksum (MD5)

5940807d21a527d340bdd657905bb581

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