“Design and Verification of a Reusable Self-Reconfigurable Gate Array Architecture

This thesis presents the design and verification of a Self-Reconfigurable Gate Array architecture (SRGA-UT) created for reuse, and available with a step-by-step tutorial and comprehensive documentation. The original SRGA [1], created at the University of Southern California, is an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to a unified on-chip configuration/data memory. The key architecture that enables the above two features is the use of a mesh of trees based interconnect with logic cells and memory blocks at the leaf nodes and identical switches at the parent nodes.

The SRGA-UT was adapted by making necessary modifications to the original design, to be implemented using the available University of Tennessee electronic design automation tools. An 8x8 array of PEs (Processing Elements) was synthesized and routed targeting a standard cell library for a 0.18 μm process. The synthesized design can store eight configuration contexts in each PE (this number can be modified by editing the Verilog files). The place and route generated a core-chip size of 5,413,300 μm^{2, and contains 354,053 number of gates. The step-by-step tutorial demonstrates that the SRGA-UT design is capable to switch context and perform memory access operations in a single clock cycle.}

ModelSim tools were used for verification and simulation at all levels, Design Compiler executed the synthesis and created the netlist design, and First Encounter SoC performed the place and route and created the delay constraints.