A 64-Channel Mixed-Signal Data Acquisition System for a Solid-State High Efficiency Neutron Detector Array

This thesis presents the design of multiple analog and digital blocks required to implement a desired solid-state data acquisition system for the High Efficiency Neutron Detector Array (HENDA) project under the Spallation Neutron Source (SNS) at Oak Ridge National Laboratory (ORNL). This system encloses and is an extension of prior work described in [1] and [2]. The first prototype chip, named Patara, contained a charge sensitive front-end amplifier [2], and a semi-Gaussian shaper with baseline restore circuitry [1]. Patara III, described in this thesis, involved the addition of the following system components; two comparators, a selectable synchronous/asynchronous digital backend, priority and binary encoders, nine LVDS drivers/receivers, three 8-bit current driven calibration DAC’s, two BGR’s, and a 99-bit serial shift register with channel test-mode circuitry. The design approach for all major blocks will be discussed along with overall system simulations. In addition, the testing procedure and associated measured results will be summarized illustrating a successful system design. This ASIC was fabricated using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-μm process available through MOSIS.