Physical design of area-array integrated circuits

The continuing drive towards more complex integrated circuits (ICs) having lower cost, more inputs or outputs (I/Os), greater operating speed, increased function per chip, and smaller device geometries has pushed the connection re-quirements beyond the capability of the traditional perimeter-lead IC package. Due to these factors, flip-chip die attach processes have been developed to support pad-limited IC designs, allowing semiconductor designers to take advantage of this technology to place pad sites in an array on the surface of the die, rather than just around the perimeter. In this dissertation, a new framework for designing an area-array IC has been developed and implemented. The I/O circuitry/buffer and the pad are separated so that the buffer can be placed anywhere in the layout. In the input data preparation stage, the hierarchy of the logic design is flattened and the necessary information is extracted from the layout and imported to the pad generation tool. The Pad generation tool operates in three stages. The first stage is a placement of the possible area-array pads on the top metal layer of the design which may contain some prerouted wires and keepout areas. The sec-ond stage is the assignment of I/O ports to their closest pads using a bipartite weighted matching algorithm. The third stage physically connects together the I/O ports to the closest pads using a modified maze router based on A* search. Finally, the resulted layout of the area-array padframe is added to the chip core to generate an area-array IC.