An analysis and implementation of state space digital filters free of limit cycles

The focus of this thesis is the elimination of constant-input limit cycles in fixed-point implementation of digital filters. Methods are discussed that produce state-space realizations free of limit cycles under constant-input conditions from realizations free of limit cycles under zero-input conditions. The first issue that was addressed is whether a realization free of limit cycles under zero-input conditions can have limit cycles under constant-input conditions. Computer simulations were presented to show that realizations free of zero-input limit cycles can have constant-input limit cycles. Four transfer functions which have constant-input limit cycles were selected for subsequent study. Implementations of these transfer functions on a Motorola DSP56000/1 family of digital signal processors were considered. By implementing these transfer functions on a Motorola DSP56000/1 simulator, it was verified that constant-input limit cycles are eliminated from the four transfer functions. To measure the computational cost of eliminating limit cycles, the limit-cycle-free implementations were compared to implementations that support limit cycles. The comparison was based on the number of processor instruction cycles required per sample processed.