Impact of packaging technology on system partioning

This thesis emphasizes concurrent consideration of the partitioning of a microelectronic circuit design into multiple dies and the selection of the appropri-ate packaging technology for implementation of the entire system. Partitioning a large design into a multichip package is a non-trivial task. Similarly, selection of the MCM packaging technology to accommodate a multichip solution can also be puzzling. The interdependencies of these two problems afford the opportuni-ty to achieve a global optimum when considered concurrently. In this work the author addresses the partitioning/MCM technology tradeoff, their interdepen-dency, and previous work in this area [1]. The SUN MicroSparc CPU is used as a demonstration vehicle and is partitioned for different MCM technologies. The preliminary results show that the optimum number of partitions and contents of each partition depend heavily on the choice of MCM technologies for a given application.