Analysis and Characterization of Single-Poly Floating Gate Devices in 0.35um PDSOI Process

The purpose of this thesis is to demonstrate a single-poly Floating Gate Device (FGD) in 0.35 m Partially Depleted Silicon On Insulator (PDSOI) process for use in analog circuits for post process trimming. Floating gate devices with different aspect ratios have been fabricated to facilitate this behavioral study in PDSOI process. Fundamentals of floating gate devices, the advantages and disadvantages of PDSOI compared to bulk CMOS with respect to single-poly floating gate devices are discussed. Various experiments on behavior and performance of threshold voltage have been conducted and its variation with programming/erasing time and amplitude has been analyzed. The single-poly FGD’s on-resistance variation and hysteresis behavior with threshold voltage has been documented. A mathematical relation between FGD’s on-resistance and threshold voltage has been experimentally derived. Intrinsic data retention has been estimated through extrapolation of experimental data. A process independent MATLAB simulation model has been successfully developed for understanding the threshold voltage time dependence characteristics. And finally, this work has shown that programmable or post-process trimmable analog circuits can be implemented in SOI using single-poly FGDs as programmable resistive elements. A SOI programmable beta-multiplier current reference has been successfully demonstrated using the singlepoly FGD as a resistive element.