Development and automation of a procedure for improved timing analysis of field-programmable gate arrays

The timing delay of a net connecting logic cells in field-programmable logic devices varies considerably (sometimes by a factor of two) depending on the specific routing resources used. The designer must analyze these delays carefully to minimize the time period required for the system clock and, hence, to maximize the speed of the system. This thesis describes a procedure, which has been automated, for improved timing analysis of these devices. This procedure will perform timing analysis with precise results after the automatic placement and routing has been completed for a design. The software was written in the C programming language specifically for the Xilinx family of devices. However, the procedure has been generalized to be readily adopted to other devices. The developed software, titled the "PATHFINDER," can be executed on an IBM-compatible personal computer.