Design of a Device-aware Memristive Neuromorphic System with Spike Timing Dependent Learning

Spiking neural networks (SNN) present a biologically plausible energy efficient learning platform by encoding data into sparse spiking events. The discovery of memristor, a nanoelectronic device, has accelerated the development of SNNs, as the inherent plasticity of the device makes it a suitable candidate to imitate a biological synapse. In spite of offering the advantages of nanoscale sizing, non-volatility, compatibility with the fabrication process, and energy efficient operation, there remain significant challenges to form and program these devices to be used in a CMOS/memristor hybrid neuromorphic system. This work introduces a forming and programming circuit along with a scan-in scheme to program both CMOS and multi-bit memristor devices. Using the formed and programmed devices, a twin memristor synapse is constructed that exhibits both excitatory and inhibitory behavior. The function of the proposed synapse as an interface between neurons is described, implementing spike-timing-dependent plasticity (STDP) based learning to update the synaptic weight. The sparse recurrent SNN built using the designed twin memristor synapse is found to have high accuracy for different data classification applications. The twin memristor synapse design is enhanced further to support crossbar based single layer spiking neuromorphic system with unsupervised learning to counter the memristive device imperfections, leveraging pulse width modulated STDP in the synapses and homeostatic plasticity in the neurons. The performance of the proposed spiking neuromorphic system was evaluated by using the network to recognize a handwritten-digits dataset, quantifying the impact of different network parameters such as the number of output neurons, training epochs, capacitors used in the design etc. Moreover, the effect of memristive device imperfections such as device parameter asymmetry, endurance degradation, array failure, fabrication process immaturity on the performance of the network was considered, demonstrating a high degree of robustness. As an application, the designed neuromorphic system was combined with a SPAD based vision sensor with Address Event Representation (AER) readout to enable efficient on-chip processing of spatio-temporal data.