Development and verification of library cells for reconfigurable logic

Champion is an Adaptive Computing System being developed as a means to translate software-based image-processing applications into equivalent hardware implementations targeted for multi-FPGA (Field Programmable Gate Array) platforms. Using Cantata, an image-processing designer can develop a Khoros workspace to implement an algorithm by connecting Khoros glyphs together. Therefore, the objectives of Champion are to parse a Khoros workspace and automatically translate the design captured by the workspace into a form that can be executed on a multi-FPGA platform. A library of hardware glyphs was developed for the Champion research project to use for its translations. It was therefore necessary to ensure the same functionality between the Khoros glyphs and the hardware glyphs. Design criteria were established so that all hardware glyphs work together in a pipelined fashion. The hardware glyphs were developed in a parameterized manner written in VHDL (Very High Speed Integrated Circuit Hardware Description Language). The VHDL code was then synthesized using the Synplify synthesis tool to generate XNF (Xilinx Netlist File) files. Each glyph was simulated using Altera Max Plus II to ensure proper functionality. After successful simulation of a hardware glyph was achieved, the glyph was executed on a Xilinx FPGA to verify the glyph’s design. Finally, the verified glyphs were collected together into a library which characterizes the glyphs by size, delay, and I/O count.