Automated evaluation and FPGA implementation of VHDL-based designs

Field Programmable Gate Arrays (FPGAs) offer the benefits of both programmable logic arrays and gate arrays. This has resulted in tremendous growth in their market, leading to the evolution of various series of FPGAs. The variety of FPGAs has created a need for software to find the best avail- able FPGA for a particular application. This thesis describes a procedure for determining the FPGA best suited for a design in terms of utilization. The proce- dure automatically evaluates and implements VHDL-based designs on the FPGAs available from different vendors. The results of the evaluation are summarized in a file. This procedure enhances the productivity of the designer. The software was written using C-shell scripts and the C programming language. It uses Viewlogic toolsets and runs on a Sun workstation.