Automated component placement in multichip modules using multiple criteria

In this thesis we study some of the approaches to placement of components (dies) in multichip modules. A simulated annealing based electrical/thermal placement tool has been developed that runs in a PVM ( Parallel Virtual Machine ) en-vironment. Placement and routing constitute the main tasks in physical design. Placement of multiple dies on an MCM substrate is a non-trivial task in which multiple criteria need to be considered simultaneously. An ideal auto-placement tool should result in the smallest layout while conforming to electrical and ther-mal requirements. This thesis describes in detail the software that has been developed to perform placement of components (dies) in an MCM with ther-mal criteria taken into consideration simultaneously along with the objective of total netlength (delay and area) minimization. By doing a simultaneous auto-placement considering both thermal and netlength objectives we see that the final netlength after optimization is higher on average by 10 percent compared to the case when only netlength minimization is done; the heat penalty however is much lower. Executing the applications in a parallel mode results in speedup by a fac-tor of eight for a 37 die, 7118 net MCM example when we use 11 Sparcstations. Our approach reduces the system design time while achieving the same quality of placement. By executing the optimization in parallel (PVM) the runtime can be substantially reduced ( factor of eight ). In addition our approach also allows a quick exploration of the design space to obtain a near optimal solution and a more uniform thermal distribution.