The development, design, and comparison of printed circuit board and multichip module representations of a DSP subsystem

A DSP Subsystem has been designed and consists of a Motorola DSP 96002 processor, 256 K-bytes of SRAM, a 128 K-byte EEPROM, a Xilinx 4010 FPGA, and an ADC. The design is represented in PCB, MCM-D, and MCM-C technologies. The three versions of the design are evaluated and compared based on cost, area, thermal constraints, and signal integrity. An evaluation of the PCB representation returned a substrate size of 15,726 mm², a high volume substrate cost of $18.97, and a system speed of 37 MHz. An evaluation of the MCM-D representation returned a substrate size of 1,369 mm², a high volume substrate cost of $60.88, and a system speed of 50 MHz. An evaluation of the MCM-C representation returned a substrate size of 1,764 mm², a high volume substrate cost of $21.95, and a system speed of 44 MHz.