Design and Implementation of an All Digital Phase Locked Loop using a Pulse Output Direct Digital Frequency Synthesizer

Phase Locked Loops (PLLs) are widely used in clock recovery and frequency synthesis. Fully Digital PLLs are more suitable for the monolithic implementation with other circuits compared to the traditional implementations of the PLLs. The All Digital PLLs are also independent of process variations and can be easily ported to different technologies.

This thesis presents the design of an All Digital Phase Locked Loop (ADPLL) using a pulse output Direct Digital Frequency Synthesizer (DDFS) and an All Digital Phase Frequency Detector (ADPFD). General design criteria are summarized for the all digital implementation in comparison to the traditional approaches and analog implementations. The design has been fabricated using 0.6-μm CMOS technology. The ADPLL has 16-bit bi nary control and can operate in the frequency range between 1 MHz and 500 MHz. The ADPLL has 50-cycles lock time and a duty cycle distortion of less than 2%. The simulation and test results of the ADPLL are also presented to verify its operation.