Development and automation of a procedure for post-layout timing analysis of integrated circuits

VLSI complex circuit designs have an increasing need of complete timing analysis tools for circuit verification. Timing constraints of post-layout information are becoming extremely vital for accomplishing a successful design. Hence, designers prefer that timing delays be computed concurrently with functional evaluations by working with estimated gate propagation times. This thesis describes ways of bridging the gap between the functional and timing simulations. It proposes a new simulation methodology, and outlines some important delay modeling methods. One procedure for post-layout timing analysis, CKTIM, is developed and automated by writing the program, Sim2Bat. This software was written in awk, sed, and C languages for the Viewlogic/Lager design and layout tools for a standard-cell library. However, the procedure has been generalized to be extendible to other libraries, such as the data-path library, and other design methodologies, such as analog design methods. The developed software executes on Sun Microsystems UNIX workstations.