A direct coupled wideband hybridized amplifier with a fast/slow loop

This thesis presents the design criteria and circuit configuration required for a direct coupled wideband amplifier using a fast/slow loop. A constant closed-loop gain is achieved from dc to the -3 dB bandwidth of the fast amplifier. Analytical expressions are derived for the voltage transfer function of the fast/slow loop. The feedback resistor relationship necessary to cancel the low-frequency time constants introduced by the slow loop are also derived. By utilizing a slow loop, the dc drift of the composite amplifier is determined by the input offset drift of an inexpensive monolithic operational amplifier. The wide bandwidth and dc stability have been achieved by combining hybrid and monolithic circuit technologies with modern

high-frequency components.

A single-ended input configuration is chosen for the fast stage since only one transistor is needed and one resistor change is sufficient to vary the closed-loop voltage gain of the fast loop, while maintaining a constant bandwidth. . A current mirror and common-base stage form the interstage connection to the complementary cascaded emitter follower output driver. The slow loop, or dc stabilization circuit, provides the bias current for the input transistor.

The experimental data includes the frequency response, step response, and dc stability of the hybridized amplifier. The amplifier has a measured closed-loop bandwidth of approximately 200 MHz. The risetime is less than 2.5 ns with less than l0% overshoot for a ± 5 volt signal into a 50-ohm load. The measured dc drift of the amplifier is 27 µV/°c referred to as the input.