Design and Verification of the Data Encryption Standard for ASICs and FPGAs

Encryption and decryption in a communication channel are used to provide security. In this thesis, the Data Encryption Standard (DES) is implemented with both FPGAs and ASICs. Different versions of FPGAs from different synthesis tools are compared. For ASIC implementation, the design space is explored to compile the design with different optimization targets like size, speed and power. Physical realizations of the design are obtained with Cadence tools. Simulations are made at each level to verify the implementations.