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  5. The development and implementation of a machine vision system for measuring perforation registration of postage stamps
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The development and implementation of a machine vision system for measuring perforation registration of postage stamps

Date Issued
May 1, 1992
Author(s)
Gleason, Shaun Scott
Advisor(s)
Donald W. Bouldin
Additional Advisor(s)
Robert E. Bodenheimer
Dragana Brzakovig
Permanent URI
https://trace.tennessee.edu/handle/20.500.14382/33510
Abstract

An on-press machine vision system was developed and implemented that measures the perforation-to-image registration of postage stamps to 0.001-in. accuracy through the use of specialized image processing algorithms and high-speed hardware. The system development can be divided into two separate stages: (1) algorithm development and (2) hardware implementation. During the development of this perforation registration system (PRS) several different measurement techniques were evaluated to solve the general problem of locating an object in a digital image to subpixel accuracies. The approach presented uses separate techniques to locate the stamp image and the position of the perforation borders. All of the investigated measurement techniques are presented, and the algorithms used in the final PRS are described in detail. The position of the stamp image is found by fitting a three-dimensional paraboloid to a normalized correlation surface to locate the stamp image to a 1/8-pixel accuracy. A separate algorithm used to locate the perforation borders to ~1/16 of a pixel is based on a least-squares fit of a line through the centers of the horizontal and vertical perforation borders. A unique image acquisition system is presented that is implemented by using front and back illumination by strobe lamps that freeze the motion of the stamps passing by a charge-injection device camera at a rate of 400 ft/min. The registration algorithms are implemented in a combination of specialized image processing hardware and a general-purpose vector accelerator that allow measurements to be made at a rate of 7 Hz. All of this hardware is under the control of a supervisory host computer.

Degree
Master of Science
Major
Electrical Engineering
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Thesis92G564.pdf

Size

7.25 MB

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Unknown

Checksum (MD5)

ba2f1bfe158e8bf0fd38f564250a1c62

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