A low noise 45-75 MHz phase-locked loop frequency synthesizer for a high performance communications receiver

Many modern high performance communications receivers utilize phase-locked loop frequency-synthesized signal sources for driving their mixers to provide excellent tuning accuracy and stability. Phase noise in these synthesizers must be low as it degrades receiver performance due to reciprocal mixing noise. A low noise phase-locked loop frequency synthesizer is described for a 0.1-30 MHz communications receiver. The synthesizer covers 45-75 MHz with 1 kHz channels and features a phase noise of -145 dBc at 20 kHz from the carrier. The excellent noise performance is obtained by using a switched inductor design for the voltage controlled oscillator.

Phase noise theory and measurement is discussed, and a phase noise test set that was used to evaluate the synthesizer noise performance is described. Phase-locked loop theory is discussed with particular emphasis on noise performance. Practical design considerations are also presented. Additionally, oscillator noise theory and design is discussed with particular emphasis on maximizing in-circuit resonator Q and minimizing circuit noise. Phase modulation noise due to active device nonlinearities and low frequency circuit noise is also discussed.

Extensive analysis is provided for the synthesizer, including several computer programs using both the FORTRAN language and the SPICE circuit analysis program. Suggestions are offered for improving the synthesizer design along with suggestions for further research in low noise signal source design.