Hierarchical clustering of digital circuits

The increased complexity of schematics has generated the need for comprehensible representation of the schematics. An algorithm to create a hierarchical representation of a flat digital schematic is presented. The algorithm is implemented in the 'C programming language. The input is a text file representation of a schematic database used by the P-CAD schematic capture package. Schematics are partitioned into modules containing 7 ± 2 blocks to facilitate comprehension. Clustering of logic symbols is done to make the algorithm independent of the person drawing the schematic. A preclustering step is incorporated to aid in the development of module partitions. The algorithm implementation operates on a personal computer.

A quality measure is used to grade the schematic partitioned. The quality measure is based on a Guassian distribution function and the average number of logic symbols per page. Several digital schematics are used as a test cases. The hierarchical algorithm's performance is analyzed by interpreting the quality measure.