Date of Award

12-1996

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

T. Vaughn Blalock

Committee Members

Robert E. Bodenheimer, James M. Rochelle

Abstract

In this work the design of a constant-fraction discriminator (CFD) fabricated in the Orbit Semiconductor l.2-Jl n-well CMOS process is presented. This timing pick-off circuit is designed for use in the readout electronics of the Lead-Scintillator subsystem of the Pioneering High Eenergy Nuclear Ion eXperiment (PHENIX) Electromagnetic Calorimeter at the Relativistic Heavy Ion Collider (RHIC). The design was driven by stringent requirements including low power consumption, small area, arrayable, low cost and a fully integratable shaping network. Various integratable CFD shaping methods are investigated, and the candidate methods chosen for fabrication were the distributed R-C delay-line shaping, lumped-element R-C shaping and Nowlin method shaping. An additional channel of ideal delay-line shaping, utilizing coaxial cable to generate delay, was fabricated and used for a reference in comparing methods. These shaping methods are compared on the basis of die area, time walk performance and timing jitter performance as implemented using the CMOS CFD presented.

Each shaping method investigated required no power from the dc supply. Die area for the distributed R-C delay-line, lumped-element R-C, Nowlin method and ideal delay-line (fraction circuit only) were 172 Jl X 70 Jl, 160 Jl X 65 Jl, 179 Jl X 53 Jl and 67 Jl X65Jl,respectively. Timewalkovera100:1dynamicrange(-2Vpeakto-20mVpeak) for these shaping methods in turn was found to be ± 175 ps, ± 150ps , ± 150 ps and ± 185 ps, respectively. Timing jitter performance with a minimum input signal (-20 mVpeak) in rms units for the four methods in turn were 65 ps, 85 ps, 100 ps and 65 ps. The average power dissipated per CFD channel was found to be approximately 12 mW.

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